J14 Pins 1-2 (near plcc32 socket)
Switches:
- SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
+ SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
01100 :: CORE = 2.5:1
10000 :: CORE = 3:1
11100 :: CORE = 3.5:1
10100 :: CORE = 4:1
01110 :: CORE = 4.5:1
- SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
+ SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
001 :: SYSCLK = 40MHz
- SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
+ SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
0100 :: 4X
0110 :: 6X
1000 :: 8X
1100 :: 12X
1110 :: 14X
0000 :: 16X
- SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
+ SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
- SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
+ SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
0100000 :: VCORE = 1.11V
SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
1 :: VCC_PLAT = 1.0V
- SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
- SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
- SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
+ SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
+ SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
+ SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
- SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
+ SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
0 :: boot from PromJet
- SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
+ SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
halves (virtual banks)
0 :: normal
- SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
- SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
+ SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
+ SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
1:1 for PD6
- SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
- SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
+ SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
+ SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
- SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
- SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
- SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
- SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
- SW6(7) = 1 CFG_MEMDEBUG = 1 ::
- SW6(8) = 1 CFG_DDRDEBUG = 1 ::
+ SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
+ SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
+ SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
+ SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
+ SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
+ SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
SW8(7) = 1 ACPWR = 1 :: non-battery
- SW8(8) = 0 CFG_IDWP = 0 :: write enable
+ SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
3. Flash U-Boot
tftp 1000000 u-boot.bin
protect off all
- erase fff00000 ffffffff
- cp.b 1000000 fff00100 80000
+ erase fff00000 +$filesize
+ cp.b 1000000 fff00000 $filesize
+
+or use tftpflash command:
+ run tftpflash
To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
tftp 1000000 u-boot.bin
- erase ffb00000 ffbfffff
- cp.b 1000000 ffb00100 80000
+ erase ffb00000 +$filesize
+ cp.b 1000000 ffb00000 $filesize
4. Memory Map
-------------
- Memory Range Device Size
+ Memory Range Device Size
------------ ------ ----
0x0000_0000 0x7fff_ffff DDR 2G
0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
0xf800_0000 0xf80f_ffff CCSR 1M
0xf810_0000 0xf81f_ffff PIXIS 1M
0xf840_0000 0xf840_3fff Stack space 32K
- 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 512M
- 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 512M
+ 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
+ 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
0xfe00_0000 0xfeff_ffff Flash(alternate)16M
0xff00_0000 0xffff_ffff Flash(boot bank)16M
+
+5. pixis_reset command
+--------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
projects / u-boot / blobdiff