2 System Components
-2.1 CPU
+2.1 CPU
Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
512MByte DDR-II memory @ 133MHz.
8 MByte Nor Flash on local bus.
2.2 PCI
A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
-
+
2.3 FPGA
Altera Cyclone-II EP2C20/35 with PCI DMA engines.
Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
MAX5381 DAC @ 0x60 for 1st digital input threshold.
LM75 @ 0x90 for temperature monitoring.
EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
- 1st image sensor interface (slave adresses depend on sensor)
+ 1st image sensor interface (slave addresses depend on sensor)
Bus2:
MAX5381 DAC @ 0x60 for 2nd digital input threshold.
- 2nd image sensor interface (slave adresses depend on sensor)
+ 2nd image sensor interface (slave addresses depend on sensor)
3 Flash layout.
2. Initrd - name is stored in "initrd_name"
3. device tree blob - name is stored in "dtb_name"
Fallback files are the flash versions.
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