OpenOCD internally. @xref{Debug Adapter Hardware}.
@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
-ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
-Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
-debugged via the GDB protocol.
+ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
+(Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
+based cores to be debugged via the GDB protocol.
@b{Flash Programming:} Flash writing is supported for external
CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
to fill in the gaps. All of the source files are provided in-tree,
listed in the Doxyfile configuration at the top of the source tree.
+@section Gerrit Review System
+
+All changes in the OpenOCD Git repository go through the web-based Gerrit
+Code Review System:
+
+@uref{http://openocd.zylin.com/}
+
+After a one-time registration and repository setup, anyone can push commits
+from their local Git repository directly into Gerrit.
+All users and developers are encouraged to review, test, discuss and vote
+for changes in Gerrit. The feedback provides the basis for a maintainer to
+eventually submit the change to the main Git repository.
+
+The @file{HACKING} file, also available as the Patch Guide in the Doxygen
+Developer Manual, contains basic information about how to connect a
+repository to Gerrit, prepare and push patches. Patch authors are expected to
+maintain their changes while they're in Gerrit, respond to feedback and if
+necessary rework and push improved versions of the change.
+
@section OpenOCD Developer Mailing List
The OpenOCD Developer Mailing List provides the primary means of
@uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
-Discuss and submit patches to this list.
-The @file{HACKING} file contains basic information about how
-to prepare patches.
-
@section OpenOCD Bug Database
During the 0.4.x release cycle the OpenOCD project team began
It is not to be confused with the FTDI based adapters that were originally fitted to their
evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
+@section USB CMSIS-DAP based
+ARM has released a interface standard called CMSIS-DAP that simplifies connecting
+debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
+
@section USB Other
@itemize @bullet
@item @b{USBprog}
Properly installing OpenOCD sets up your operating system to grant it access
to the debug adapters. On Linux, this usually involves installing a file
-in @file{/etc/udev/rules.d,} so OpenOCD has permissions. MS-Windows needs
+in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
+that works for many common adapters is shipped with OpenOCD in the
+@file{contrib} directory. MS-Windows needs
complex and confusing driver configuration for every peripheral. Such issues
are unique to each operating system, and are not detailed in this User's Guide.
The @code{init_boards} procedure is a similar concept concerning board config files
(@xref{theinitboardprocedure,,The init_board procedure}.)
+@anchor{theinittargeteventsprocedure}
+@subsection The init_target_events procedure
+@cindex init_target_events procedure
+
+A special procedure called @code{init_target_events} is run just after
+@code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
+procedure}.) and before @code{init_board}
+(@xref{theinitboardprocedure,,The init_board procedure}.) It is used
+to set up default target events for the targets that do not have those
+events already assigned.
+
@subsection ARM Core Specific Hacks
If the chip has a DCC, enable it. If the chip is an ARM9 with some
@c chooses among list of bit configs ... only one option
@end deffn
+@deffn {Interface Driver} {cmsis-dap}
+ARM CMSIS-DAP compliant based adapter.
+
+@deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
+The vendor ID and product ID of the CMSIS-DAP device. If not specified
+the driver will attempt to auto detect the CMSIS-DAP device.
+Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
+@example
+cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
+@end example
+@end deffn
+
+@deffn {Command} {cmsis-dap info}
+Display various device information, like hardware version, firmware version, current bus status.
+@end deffn
+@end deffn
+
@deffn {Interface Driver} {dummy}
A dummy software-only driver for debugging.
@end deffn
No parameters: displays current settings.
@end deffn
+@subsection CMSIS-DAP Transport
+@cindex CMSIS-DAP
+CMSIS-DAP is an ARM-specific transport that is used to connect to
+compilant debuggers.
+
@subsection SPI Transport
@cindex SPI
@cindex Serial Peripheral Interface
TAPs serve many roles, including:
@itemize @bullet
-@item @b{Debug Target} A CPU TAP can be used as a GDB debug target
+@item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
@item @b{Flash Programming} Some chips program the flash directly via JTAG.
Others do it indirectly, making a CPU do it.
@item @b{Program Download} Using the same CPU support GDB uses,
start running that code.
@item @b{Boundary Scan} Most chips support boundary scan, which
helps test for board assembly problems like solder bridges
-and missing connections
+and missing connections.
@end itemize
OpenOCD must know about the active TAPs on your board(s).
@cindex scan chain
TAPs are part of a hardware @dfn{scan chain},
-which is daisy chain of TAPs.
+which is a daisy chain of TAPs.
They also need to be added to
OpenOCD's software mirror of that hardware list,
giving each member a name and associating other data with it.
OpenOCD can detect some of that information, but not all
of it. @xref{autoprobing,,Autoprobing}.
-Unfortunately those TAPs can't always be autoconfigured,
+Unfortunately, those TAPs can't always be autoconfigured,
because not all devices provide good support for that.
JTAG doesn't require supporting IDCODE instructions, and
chips with JTAG routers may not link TAPs into the chain
Board configuration files combine all the targets on a board,
and so forth.
Note that @emph{the order in which TAPs are declared is very important.}
-It must match the order in the JTAG scan chain, both inside
-a single chip and between them.
+That declaration order must match the order in the JTAG scan chain,
+both inside a single chip and between them.
@xref{faqtaporder,,FAQ TAP Order}.
For example, the ST Microsystems STR912 chip has
jtag newtap str912 bs ... params ...
@end example
-Actual config files use a variable instead of literals like
-@option{str912}, to support more than one chip of each type.
-@xref{Config File Guidelines}.
+Actual config files typically use a variable such as @code{$_CHIPNAME}
+instead of literals like @option{str912}, to support more than one chip
+of each type. @xref{Config File Guidelines}.
@deffn Command {jtag names}
Returns the names of all current TAPs in the scan chain.
name rules: start with an alphabetic character, then numbers
and underscores are OK; while others (including dots!) are not.
-@quotation Tip
-In older code, JTAG TAPs were numbered from 0..N.
-This feature is still present.
-However its use is highly discouraged, and
-should not be relied on; it will be removed by mid-2010.
-Update all of your scripts to use TAP names rather than numbers,
-by paying attention to the runtime warnings they trigger.
-Using TAP numbers in target configuration scripts prevents
-reusing those scripts on boards with multiple targets.
-@end quotation
-
@section TAP Declaration Commands
@c shouldn't this be(come) a {Config Command}?
and should follow this convention:
@itemize @bullet
-@item @code{bs} -- For boundary scan if this is a seperate TAP;
+@item @code{bs} -- For boundary scan if this is a separate TAP;
@item @code{cpu} -- The main CPU of the chip, alternatively
@code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
-@code{arm1} and @code{arm2} on chips two ARMs, and so forth;
+@code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
@item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
@item @code{flash} -- If the chip has a flash TAP, like the str912;
-@item @code{jrc} -- For JTAG route controller (example: the ICEpick modules
+@item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
-@item @code{tap} -- Should be used only FPGA or CPLD like devices
+@item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
with a single TAP;
@item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
@item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
-For example, the Freescale IMX31 has a SDMA (Smart DMA) with
+For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
a JTAG TAP; that TAP should be named @code{sdma}.
@end itemize
@itemize @bullet
@item @code{-disable} (or @code{-enable})
@*Use the @code{-disable} parameter to flag a TAP which is not
-linked in to the scan chain after a reset using either TRST
+linked into the scan chain after a reset using either TRST
or the JTAG state machine's @sc{reset} state.
You may use @code{-enable} to highlight the default state
(the TAP is linked in).
@xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
-@item @code{-expected-id} @var{number}
+@item @code{-expected-id} @var{NUMBER}
@*A non-zero @var{number} represents a 32-bit IDCODE
which you expect to find when the scan chain is examined.
These codes are not required by all JTAG devices.
JTAG requires the two LSBs of this value to be 01.
By default, @code{-ircapture} and @code{-irmask} are set
up to verify that two-bit value. You may provide
-additional bits, if you know them, or indicate that
+additional bits if you know them, or indicate that
a TAP doesn't conform to the JTAG specification.
@item @code{-irmask} @var{NUMBER}
@*A mask used with @code{-ircapture}
@section Other TAP commands
-@deffn Command {jtag cget} dotted.name @option{-event} name
-@deffnx Command {jtag configure} dotted.name @option{-event} name string
+@deffn Command {jtag cget} dotted.name @option{-event} event_name
+@deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
At this writing this TAP attribute
mechanism is used only for event handling.
(It is not a direct analogue of the @code{cget}/@code{configure}
by issuing the relevant JTAG commands.
@end itemize
-If you need some action after each JTAG reset, which isn't actually
+If you need some action after each JTAG reset which isn't actually
specific to any TAP (since you can't yet trust the scan chain's
contents to be accurate), you might:
In some systems, a @dfn{JTAG Route Controller} (JRC)
is used to enable and/or disable specific JTAG TAPs.
-Many ARM based chips from Texas Instruments include
-an ``ICEpick'' module, which is a JRC.
+Many ARM-based chips from Texas Instruments include
+an ``ICEPick'' module, which is a JRC.
Such chips include DaVinci and OMAP3 processors.
A given TAP may not be visible until the JRC has been
@item @b{gdb-end}
@* When the target has halted and GDB is not doing anything (see early halt)
@item @b{gdb-flash-erase-start}
-@* Before the GDB flash process tries to erase the flash
+@* Before the GDB flash process tries to erase the flash (default is
+@code{reset init})
@item @b{gdb-flash-erase-end}
@* After the GDB flash process has finished erasing the flash
@item @b{gdb-flash-write-start}
@* Before GDB writes to the flash
@item @b{gdb-flash-write-end}
-@* After GDB writes to the flash
+@* After GDB writes to the flash (default is @code{reset halt})
@item @b{gdb-start}
@* Before the target steps, gdb is trying to start/resume the target
@item @b{halted}
@end deffn
+@deffn {Flash Driver} nrf51
+All members of the nRF51 microcontroller families from Nordic Semiconductor
+include internal flash and use ARM Cortex-M0 core.
+
+@example
+flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
+@end example
+
+Some nrf51-specific commands are defined:
+
+@deffn Command {nrf51 mass_erase}
+Erases the contents of the code memory and user information
+configuration registers as well. It must be noted that this command
+works only for chips that do not have factory pre-programmed region 0
+code.
+@end deffn
+@end deffn
@section mFlash
by using @command{targets} command with the name of the
target which should become current.
-@deffn Command reg [(number|name) [value]]
+@deffn Command reg [(number|name) [(value|'force')]]
Access a single register by @var{number} or by its @var{name}.
The target must generally be halted before access to CPU core
registers is allowed. Depending on the hardware, some other
are flagged as such.
@emph{With number/name}: display that register's value.
+Use @var{force} argument to read directly from the target,
+bypassing any internal cache.
@emph{With both number/name and value}: set register's value.
Writes may be held in a writeback cache internal to OpenOCD,
@xref{targetevents,,Target Events}.
@end deffn
+@section Intel Architecture
+
+Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
+(Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
+Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
+software debug and the CLTAP is used for SoC level operations.
+Useful docs are here: https://communities.intel.com/community/makers/documentation
+@itemize
+@item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
+@item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
+@item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
+@end itemize
+
+@subsection x86 32-bit specific commands
+The three main address spaces for x86 are memory, I/O and configuration space.
+These commands allow a user to read and write to the 64Kbyte I/O address space.
+
+@deffn Command {x86_32 idw} address
+Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 idh} address
+Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 idb} address
+Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 iww} address
+Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 iwh} address
+Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
+@end deffn
+
+@deffn Command {x86_32 iwb} address
+Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
+@end deffn
+
@section OpenRISC Architecture
The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
There is often a need to stress-test random access memory (RAM) for
errors. OpenOCD comes with a Tcl implementation of well-known memory
-testing procedures allowing to detect all sorts of issues with
+testing procedures allowing the detection of all sorts of issues with
electrical wiring, defective chips, PCB layout and other common
hardware problems.
-To use them you usually need to initialise your RAM controller first,
+To use them, you usually need to initialise your RAM controller first;
consult your SoC's documentation to get the recommended list of
register operations and translate them to the corresponding
@command{mww}/@command{mwb} commands.
@section Firmware recovery helpers
@cindex Firmware recovery
-OpenOCD includes an easy-to-use script to faciliate mass-market
+OpenOCD includes an easy-to-use script to facilitate mass-market
devices recovery with JTAG.
For quickstart instructions run:
@node TFTP
@chapter TFTP
@cindex TFTP
-If OpenOCD runs on an embedded host(as ZY1000 does), then TFTP can
+If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
be used to access files on PCs (either the developer's PC or some other PC).
The way this works on the ZY1000 is to prefix a filename by
@node GDB and OpenOCD
@chapter GDB and OpenOCD
@cindex GDB
-OpenOCD complies with the remote gdbserver protocol, and as such can be used
+OpenOCD complies with the remote gdbserver protocol and, as such, can be used
to debug remote targets.
Setting up GDB to work with OpenOCD can involve several components:
With the remote protocol, GDB sessions start a little differently
than they do when you're debugging locally.
-Here's an examples showing how to start a debug session with a
+Here's an example showing how to start a debug session with a
small ARM program.
In this case the program was linked to be loaded into SRAM on a Cortex-M3.
Most programs would be written into flash (address 0) and run from there.
that the OpenOCD option @command{gdb_breakpoint_override} is not required when
using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
-To view the configured memory map in GDB, use the GDB command @option{info mem}
+To view the configured memory map in GDB, use the GDB command @option{info mem}.
All other unassigned addresses within GDB are treated as RAM.
GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
@end itemize
@quotation Note
-Before an RTOS can be detected it must export certain symbols otherwise it cannot be used by
-OpenOCD. Below is a list of the required symbols for each supported RTOS.
+Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
+be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
@end quotation
@table @code
@cindex Tcl scripts
@section API rules
-The commands are stateless. E.g. the telnet command line has a concept
-of currently active target, the Tcl API proc's take this sort of state
-information as an argument to each proc.
+Tcl commands are stateless; e.g. the @command{telnet} command has
+a concept of currently active target, the Tcl API proc's take this sort
+of state information as an argument to each proc.
There are three main types of return values: single value, name value
pair list and lists.
Name value pair. The proc 'foo' below returns a name/value pair
list.
-@verbatim
-
- > set foo(me) Duane
- > set foo(you) Oyvind
- > set foo(mouse) Micky
- > set foo(duck) Donald
+@example
+> set foo(me) Duane
+> set foo(you) Oyvind
+> set foo(mouse) Micky
+> set foo(duck) Donald
+@end example
If one does this:
- > set foo
+@example
+> set foo
+@end example
The result is:
- me Duane you Oyvind mouse Micky duck Donald
+@example
+me Duane you Oyvind mouse Micky duck Donald
+@end example
Thus, to get the names of the associative array is easy:
- foreach { name value } [set foo] {
- puts "Name: $name, Value: $value"
- }
+@verbatim
+foreach { name value } [set foo] {
+ puts "Name: $name, Value: $value"
+}
@end verbatim
-Lists returned must be relatively small. Otherwise a range
+Lists returned should be relatively small. Otherwise, a range
should be passed in to the proc in question.
@section Internal low-level Commands
-By low-level, the intent is a human would not directly use these commands.
+By "low-level," we mean commands that a human would typically not
+invoke directly.
-Low-level commands are (should be) prefixed with "ocd_", e.g.
+Some low-level commands need to be prefixed with "ocd_"; e.g.
@command{ocd_flash_banks}
-is the low level API upon which @command{flash banks} is implemented.
+is the low-level API upon which @command{flash banks} is implemented.
@itemize @bullet
@item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
@item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
Return information about the flash banks
+
+@item @b{capture} <@var{command}>
+
+Run <@var{command}> and return full log output that was produced during
+its execution. Example:
+
+@example
+> capture "reset init"
+@end example
+
@end itemize
OpenOCD commands can consist of two words, e.g. "flash banks". The
@item @b{cygwin} Running under Cygwin
@item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
@item @b{freebsd} Running under FreeBSD
+@item @b{openbsd} Running under OpenBSD
+@item @b{netbsd} Running under NetBSD
@item @b{linux} Linux is the underlying operating sytem
@item @b{mingw32} Running under MingW32
@item @b{winxx} Built using Microsoft Visual Studio
+@item @b{ecos} Running under eCos
@item @b{other} Unknown, none of the above.
@end itemize
is jim, not real tcl).
@end quotation
+@section Tcl RPC server
+@cindex RPC
+
+OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
+commands and receive the results.
+
+To access it, your application needs to connect to a configured TCP port
+(see @command{tcl_port}). Then it can pass any string to the
+interpreter terminating it with @code{0x1a} and wait for the return
+value (it will be terminated with @code{0x1a} as well). This can be
+repeated as many times as desired without reopening the connection.
+
+Remember that most of the OpenOCD commands need to be prefixed with
+@code{ocd_} to get the results back. Sometimes you might also need the
+@command{capture} command.
+
+See @file{contrib/rpc_examples/} for specific client implementations.
+
@node FAQ
@chapter FAQ
@cindex faq