]> git.sur5r.net Git - u-boot/blobdiff - drivers/bootcount/bootcount_davinci.c
clk: Add Actions Semi OWL clock support
[u-boot] / drivers / bootcount / bootcount_davinci.c
index efa4d42cbf4ca7181ca83ebb6909104e2cf6ecbe..7101ad9413ecf60bc08958214a1790738afdef30 100644 (file)
@@ -1,13 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2011
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
- * SPDX-License-Identifier:    GPL-2.0+
+ * A bootcount driver for the RTC IP block found on many TI platforms.
+ * This requires the RTC clocks, etc, to be enabled prior to use and
+ * not all boards with this IP block on it will have the RTC in use.
  */
 
 #include <bootcount.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/davinci_misc.h>
+#include <asm/davinci_rtc.h>
 
 void bootcount_store(ulong a)
 {
@@ -15,23 +17,25 @@ void bootcount_store(ulong a)
                (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
 
        /*
-        * write RTC kick register to enable write
-        * for RTC Scratch registers. Scratch0 and 1 are
-        * used for bootcount values.
+        * write RTC kick registers to enable write
+        * for RTC Scratch registers. Scratch register 2 is
+        * used for bootcount value.
         */
        writel(RTC_KICK0R_WE, &reg->kick0r);
        writel(RTC_KICK1R_WE, &reg->kick1r);
-       raw_bootcount_store(&reg->scratch0, a);
-       raw_bootcount_store(&reg->scratch1, BOOTCOUNT_MAGIC);
+       raw_bootcount_store(&reg->scratch2,
+                           (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff));
 }
 
 ulong bootcount_load(void)
 {
+       unsigned long val;
        struct davinci_rtc *reg =
                (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR;
 
-       if (raw_bootcount_load(&reg->scratch1) != BOOTCOUNT_MAGIC)
+       val = raw_bootcount_load(&reg->scratch2);
+       if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
                return 0;
        else
-               return raw_bootcount_load(&reg->scratch0);
+               return val & 0x0000ffff;
 }