ARM64: zynqmp: Adjust to new SMC interface to get silicon version

[u-boot] / drivers / clk / at91 / clk-peripheral.c

diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 16688e90b417fc1ed9a3996f848f7be606eb822c..e1ed447133e077201c5b7f638ef23b5e6d0850b8 100644 (file)
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -16,7 +16,32 @@
 #define PERIPHERAL_ID_MAX      31
 #define PERIPHERAL_MASK(id)    (1 << ((id) & PERIPHERAL_ID_MAX))
 
-static int sam9x5_periph_clk_enable(struct clk *clk)
+/**
+ * sam9x5_periph_clk_bind() - for the periph clock driver
+ * Recursively bind its children as clk devices.
+ *
+ * @return: 0 on success, or negative error code on failure
+ */
+static int sam9x5_periph_clk_bind(struct udevice *dev)
+{
+       return at91_clk_sub_device_bind(dev, "periph-clk");
+}
+
+static const struct udevice_id sam9x5_periph_clk_match[] = {
+       { .compatible = "atmel,at91sam9x5-clk-peripheral" },
+       {}
+};
+
+U_BOOT_DRIVER(sam9x5_periph_clk) = {
+       .name = "sam9x5-periph-clk",
+       .id = UCLASS_MISC,
+       .of_match = sam9x5_periph_clk_match,
+       .bind = sam9x5_periph_clk_bind,
+};
+
+/*---------------------------------------------------------*/
+
+static int periph_clk_enable(struct clk *clk)
 {
        struct pmc_platdata *plat = dev_get_platdata(clk->dev);
        struct at91_pmc *pmc = plat->reg_base;
@@ -30,31 +55,36 @@ static int sam9x5_periph_clk_enable(struct clk *clk)
        return 0;
 }
 
-static struct clk_ops sam9x5_periph_clk_ops = {
-       .enable = sam9x5_periph_clk_enable,
-};
-
-static int sam9x5_periph_clk_bind(struct udevice *dev)
+static ulong periph_get_rate(struct clk *clk)
 {
-       return at91_pmc_clk_node_bind(dev);
-}
+       struct udevice *dev;
+       struct clk clk_dev;
+       ulong clk_rate;
+       int ret;
 
-static int sam9x5_periph_clk_probe(struct udevice *dev)
-{
-       return at91_pmc_core_probe(dev);
+       dev = dev_get_parent(clk->dev);
+
+       ret = clk_get_by_index(dev, 0, &clk_dev);
+       if (ret)
+               return ret;
+
+       clk_rate = clk_get_rate(&clk_dev);
+
+       clk_free(&clk_dev);
+
+       return clk_rate;
 }
 
-static const struct udevice_id sam9x5_periph_clk_match[] = {
-       { .compatible = "atmel,at91sam9x5-clk-peripheral" },
-       {}
+static struct clk_ops periph_clk_ops = {
+       .of_xlate = at91_clk_of_xlate,
+       .enable = periph_clk_enable,
+       .get_rate = periph_get_rate,
 };
 
-U_BOOT_DRIVER(sam9x5_periph_clk) = {
-       .name = "sam9x5-periph-clk",
-       .id = UCLASS_CLK,
-       .of_match = sam9x5_periph_clk_match,
-       .bind = sam9x5_periph_clk_bind,
-       .probe = sam9x5_periph_clk_probe,
+U_BOOT_DRIVER(clk_periph) = {
+       .name   = "periph-clk",
+       .id     = UCLASS_CLK,
        .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
-       .ops = &sam9x5_periph_clk_ops,
+       .probe = at91_clk_probe,
+       .ops    = &periph_clk_ops,
 };