sf: add Gigadevice gd25q16c entry

[u-boot] / drivers / clk / clk-hsdk-cgu.c

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index d9da477f4e6aa0819ff1e95432c98b09a0c61984..56ef08c032b99b500aa629b065b1df012bf09820 100644 (file)
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -59,8 +59,6 @@
  *                     |---------------------------->
  */
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define CGU_ARC_IDIV           0x080
 #define CGU_TUN_IDIV_TUN       0x380
 #define CGU_TUN_IDIV_ROM       0x390
@@ -492,7 +490,7 @@ static ulong pll_set(struct clk *sclk, ulong rate)
                }
        }
 
-       pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE);
+       pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE);
 
        return -EINVAL;
 }
@@ -623,14 +621,14 @@ static ulong idiv_set(struct clk *sclk, ulong rate)
        }
 
        if (div_factor & ~CGU_IDIV_MASK) {
-               pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n",
+               pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
                       rate, parent_rate, div_factor, CGU_IDIV_MASK);
 
                div_factor = CGU_IDIV_MASK;
        }
 
        if (div_factor == 0) {
-               pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n",
+               pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
                       rate, parent_rate, div_factor);
 
                div_factor = 1;
@@ -716,6 +714,6 @@ U_BOOT_DRIVER(hsdk_cgu_clk) = {
        .id = UCLASS_CLK,
        .of_match = hsdk_cgu_clk_id,
        .probe = hsdk_cgu_clk_probe,
-       .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
+       .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
        .ops = &hsdk_cgu_ops,
 };