/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
+#include <clk-uclass.h>
#include <dm.h>
+#include <dt-structs.h>
#include <errno.h>
-#include <dm/lists.h>
-#include <dm/root.h>
-DECLARE_GLOBAL_DATA_PTR;
+static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
+{
+ return (const struct clk_ops *)dev->driver->ops;
+}
-ulong clk_get_rate(struct udevice *dev)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+# if CONFIG_IS_ENABLED(OF_PLATDATA)
+int clk_get_by_index_platdata(struct udevice *dev, int index,
+ struct phandle_1_arg *cells, struct clk *clk)
{
- struct clk_ops *ops = clk_get_ops(dev);
+ int ret;
- if (!ops->get_rate)
+ if (index != 0)
return -ENOSYS;
+ ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
+ if (ret)
+ return ret;
+ clk->id = cells[0].arg[0];
- return ops->get_rate(dev);
+ return 0;
}
+# else
+static int clk_of_xlate_default(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ if (args->args_count > 1) {
+ debug("Invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = args->args[0];
+ else
+ clk->id = 0;
-ulong clk_set_rate(struct udevice *dev, ulong rate)
+ return 0;
+}
+
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
- struct clk_ops *ops = clk_get_ops(dev);
+ int ret;
+ struct ofnode_phandle_args args;
+ struct udevice *dev_clk;
+ const struct clk_ops *ops;
- if (!ops->set_rate)
- return -ENOSYS;
+ debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
+
+ assert(clk);
+ clk->dev = NULL;
+
+ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+ index, &args);
+ if (ret) {
+ debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
+ if (ret) {
+ debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ clk->dev = dev_clk;
+
+ ops = clk_dev_ops(dev_clk);
- return ops->set_rate(dev, rate);
+ if (ops->of_xlate)
+ ret = ops->of_xlate(clk, &args);
+ else
+ ret = clk_of_xlate_default(clk, &args);
+ if (ret) {
+ debug("of_xlate() failed: %d\n", ret);
+ return ret;
+ }
+
+ return clk_request(dev_clk, clk);
}
+# endif /* OF_PLATDATA */
-int clk_enable(struct udevice *dev, int periph)
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
- struct clk_ops *ops = clk_get_ops(dev);
+ int index;
- if (!ops->enable)
+ debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
+ clk->dev = NULL;
+
+ index = dev_read_stringlist_search(dev, "clock-names", name);
+ if (index < 0) {
+ debug("fdt_stringlist_search() failed: %d\n", index);
+ return index;
+ }
+
+ return clk_get_by_index(dev, index, clk);
+}
+
+int clk_release_all(struct clk *clk, int count)
+{
+ int i, ret;
+
+ for (i = 0; i < count; i++) {
+ debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
+
+ /* check if clock has been previously requested */
+ if (!clk[i].dev)
+ continue;
+
+ ret = clk_disable(&clk[i]);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ ret = clk_free(&clk[i]);
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
+#endif /* OF_CONTROL */
+
+int clk_request(struct udevice *dev, struct clk *clk)
+{
+ const struct clk_ops *ops = clk_dev_ops(dev);
+
+ debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
+
+ clk->dev = dev;
+
+ if (!ops->request)
+ return 0;
+
+ return ops->request(clk);
+}
+
+int clk_free(struct clk *clk)
+{
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ if (!ops->free)
+ return 0;
+
+ return ops->free(clk);
+}
+
+ulong clk_get_rate(struct clk *clk)
+{
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ if (!ops->get_rate)
return -ENOSYS;
- return ops->enable(dev, periph);
+ return ops->get_rate(clk);
}
-ulong clk_get_periph_rate(struct udevice *dev, int periph)
+ulong clk_set_rate(struct clk *clk, ulong rate)
{
- struct clk_ops *ops = clk_get_ops(dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
- if (!ops->get_periph_rate)
+ debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+
+ if (!ops->set_rate)
return -ENOSYS;
- return ops->get_periph_rate(dev, periph);
+ return ops->set_rate(clk, rate);
}
-ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+int clk_enable(struct clk *clk)
{
- struct clk_ops *ops = clk_get_ops(dev);
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+ debug("%s(clk=%p)\n", __func__, clk);
- if (!ops->set_periph_rate)
+ if (!ops->enable)
return -ENOSYS;
- return ops->set_periph_rate(dev, periph, rate);
+ return ops->enable(clk);
}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
+int clk_disable(struct clk *clk)
{
- int ret;
-#ifdef CONFIG_SPL_BUILD
- u32 cell[2];
+ const struct clk_ops *ops = clk_dev_ops(clk->dev);
- if (index != 0)
+ debug("%s(clk=%p)\n", __func__, clk);
+
+ if (!ops->disable)
return -ENOSYS;
- assert(*clk_devp);
- ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
- if (ret)
- return ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
- cell, 2);
- if (ret)
- return ret;
- return cell[1];
-#else
- struct fdtdec_phandle_args args;
-
- assert(*clk_devp);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
- "clocks", "#clock-cells", 0, index,
- &args);
- if (ret) {
- debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
- __func__, ret);
- return ret;
- }
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, clk_devp);
- if (ret) {
- debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
- __func__, ret);
- return ret;
- }
- return args.args_count > 0 ? args.args[0] : 0;
-#endif
+ return ops->disable(clk);
}
-#endif
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
projects / u-boot / blobdiff