ata: ahci_mvebu: a8040 a0: remove bad port register offsets workarounds

[u-boot] / drivers / clk / clk_fixed_rate.c

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 797e5379075da87e5dac71ed7d61106c8dd9fbff..d8d9f86c8642c927bce696ab97d111090895d8d0 100644 (file)
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -1,14 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <clk-uclass.h>
-#include <dm/device.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <dm.h>
 
 struct clk_fixed_rate {
        unsigned long fixed_rate;
@@ -30,9 +27,10 @@ const struct clk_ops clk_fixed_rate_ops = {
 
 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
        to_clk_fixed_rate(dev)->fixed_rate =
-                               fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-                                              "clock-frequency", 0);
+               dev_read_u32_default(dev, "clock-frequency", 0);
+#endif
 
        return 0;
 }