rockchip: gpio: Read the GPIO value correctly

[u-boot] / drivers / clk / clk_rk3288.c

diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index df5c38cf7258ae81db79f149f416f8b1ea625df1..5a8f175e4b062d33811011fb98c9f913361fe4b6 100644 (file)
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -15,7 +15,9 @@
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/hardware.h>
 #include <dt-bindings/clock/rk3288-cru.h>
+#include <dm/device-internal.h>
 #include <dm/lists.h>
+#include <dm/uclass-internal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -139,6 +141,37 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
+int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
+{
+       struct udevice *dev;
+
+       for (uclass_find_first_device(UCLASS_CLK, &dev);
+            dev;
+            uclass_find_next_device(&dev)) {
+               struct rk3288_clk_plat *plat = dev_get_platdata(dev);
+
+               if (plat->clk_id == clk_id) {
+                       *devp = dev;
+                       return device_probe(dev);
+               }
+       }
+
+       return -ENODEV;
+}
+
+void *rockchip_get_cru(void)
+{
+       struct rk3288_clk_priv *priv;
+       struct udevice *dev;
+       int ret;
+
+       ret = rkclk_get_clk(CLK_GENERAL, &dev);
+       if (ret)
+               return ERR_PTR(ret);
+       priv = dev_get_priv(dev);
+       return priv->cru;
+}
+
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
                         const struct pll_div *div)
 {
@@ -515,14 +548,14 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
        ulong new_rate, gclk_rate;
        int ret;
 
-       ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+       ret = rkclk_get_clk(CLK_GENERAL, &gclk);
        if (ret)
                return ret;
        gclk_rate = clk_get_rate(gclk);
        switch (periph) {
        case HCLK_EMMC:
+       case HCLK_SDMMC:
        case HCLK_SDIO0:
-       case HCLK_SDIO1:
                new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
                break;
        case SCLK_SPI0:
@@ -551,7 +584,7 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
        ulong new_rate, gclk_rate;
        int ret;
 
-       ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &gclk);
+       ret = rkclk_get_clk(CLK_GENERAL, &gclk);
        if (ret)
                return ret;
        gclk_rate = clk_get_rate(gclk);