/*
- * (C) Copyright 2017
- * Vikas Manocha, <vikas.manocha@st.com>
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
/* Configure the main PLL */
- uint32_t pllcfgr = 0;
- pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
- pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
- pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
- pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
- pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
- writel(pllcfgr, ®s->pllcfgr);
+ setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
+ sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT);
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
+ sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT);
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
+ ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
+ clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
+ sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
/* Enable the main PLL */
setbits_le32(®s->cr, RCC_CR_PLLON);
return sysclk >>= shift;
break;
default:
- error("clock index %ld out of range\n", clk->id);
+ pr_err("clock index %ld out of range\n", clk->id);
return -EINVAL;
break;
}