static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
-static const resource_size_t zynqmp_iou_clkc_base = 0xff180000;
/* Full power domain clocks */
#define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
#define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
#define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
#define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
-#define IOU_SLCR_GEM_CLK_CTRL (zynqmp_iou_clkc_base + 0x308)
-#define IOU_SLCR_CAN_MIO_CTRL (zynqmp_iou_clkc_base + 0x304)
-#define IOU_SLCR_WDT_CLK_SEL (zynqmp_iou_clkc_base + 0x300)
#define ZYNQ_CLK_MAXDIV 0x3f
#define CLK_CTRL_DIV1_SHIFT 16
int ret;
ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
- if (ret)
- panic("%s mio read fail\n", __func__);
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
if (clk_ctrl & PLLCTRL_BYPASS_MASK)
freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
u32 clk_ctrl, div;
enum zynqmp_clk pll;
int ret;
+ unsigned long pllrate;
ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
- if (ret)
- panic("%s mio read fail\n", __func__);
-
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
+ pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+ if (IS_ERR_VALUE(pllrate))
+ return pllrate;
- return DIV_ROUND_CLOSEST(zynqmp_clk_get_pll_rate(priv, pll), div);
+ return DIV_ROUND_CLOSEST(pllrate, div);
}
static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
u32 clk_ctrl, div;
enum zynqmp_clk pll;
int ret;
+ ulong pllrate;
ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
- if (ret)
- panic("%s mio read fail\n", __func__);
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
+ pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+ if (IS_ERR_VALUE(pllrate))
+ return pllrate;
- return DIV_ROUND_CLOSEST(zynqmp_clk_get_pll_rate(priv, pll), div);
+ return DIV_ROUND_CLOSEST(pllrate, div);
}
static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
u32 clk_ctrl, div0;
u32 div1 = 1;
int ret;
+ ulong pllrate;
ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
- if (ret)
- panic("%s mio read fail\n", __func__);
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
if (!div0)
}
pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
+ pllrate = zynqmp_clk_get_pll_rate(priv, pll);
+ if (IS_ERR_VALUE(pllrate))
+ return pllrate;
return
DIV_ROUND_CLOSEST(
- DIV_ROUND_CLOSEST(
- zynqmp_clk_get_pll_rate(priv, pll), div0),
- div1);
+ DIV_ROUND_CLOSEST(pllrate, div0), div1);
}
static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
reg = zynqmp_clk_get_register(id);
ret = zynqmp_mmio_read(reg, &clk_ctrl);
- if (ret)
- panic("%s mio read fail\n", __func__);
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
+ if (IS_ERR_VALUE(pll_rate))
+ return pll_rate;
+
clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
if (two_divs) {
clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
- if (ret)
- panic("%s mio write fail\n", __func__);
+ if (ret) {
+ printf("%s mio write fail\n", __func__);
+ return -EIO;
+ }
return new_rate;
}
clk_free(&clk);
if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO))
+ (rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO))
printf("%10s%20s\n", name, "unknown");
else
printf("%10s%20lu\n", name, rate);