clk: renesas: Make clk_ids per-driver

[u-boot] / drivers / clk / renesas / r8a7795-cpg-mssr.c

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 58eb0732019b1e0f7df52d510225e15c5fc30a4b..ecbb9b31de797d35f9fa8b72cf154a5ccfe509ae 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -19,6 +19,36 @@
 
 #include "renesas-cpg-mssr.h"
 
+enum clk_ids {
+       /* Core Clock Outputs exported to DT */
+       LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
+
+       /* External Input Clocks */
+       CLK_EXTAL,
+       CLK_EXTALR,
+
+       /* Internal Core Clocks */
+       CLK_MAIN,
+       CLK_PLL0,
+       CLK_PLL1,
+       CLK_PLL2,
+       CLK_PLL3,
+       CLK_PLL4,
+       CLK_PLL1_DIV2,
+       CLK_PLL1_DIV4,
+       CLK_S0,
+       CLK_S1,
+       CLK_S2,
+       CLK_S3,
+       CLK_SDSRC,
+       CLK_RPCSRC,
+       CLK_SSPSRC,
+       CLK_RINT,
+
+       /* Module Clocks */
+       MOD_CLK_BASE
+};
+
 static const struct cpg_core_clk r8a7795_core_clks[] = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
@@ -252,6 +282,9 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = {
        .mstp_table_size        = ARRAY_SIZE(r8a7795_mstp_table),
        .reset_node             = "renesas,r8a7795-rst",
        .extalr_node            = "extalr",
+       .mod_clk_base           = MOD_CLK_BASE,
+       .clk_extal_id           = CLK_EXTAL,
+       .clk_extalr_id          = CLK_EXTALR,
 };
 
 static const struct udevice_id r8a7795_clk_ids[] = {