clk: renesas: Add PE clock handling

[u-boot] / drivers / clk / renesas / rcar-gen3-cpg.h

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 2f410df42afced2cd16a19873f7cc43c83b1ae84..58e71f363c895e957c387f30f0a85ae6e7f2527f 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -31,8 +31,9 @@ enum rcar_gen3_clk_types {
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
                    _div_clean) \
-       DEF_BASE(_name, _id, CLK_TYPE_FF,                       \
-                (_parent_clean), .div = (_div_clean), 1)
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,                  \
+                (_parent_sscg) << 16 | (_parent_clean),        \
+                .div = (_div_sscg) << 16 | (_div_clean))
 
 struct rcar_gen3_cpg_pll_config {
        u8 extal_div;
@@ -49,6 +50,7 @@ struct gen3_clk_priv {
        struct cpg_mssr_info    *info;
        struct clk              clk_extal;
        struct clk              clk_extalr;
+       bool                    sscg;
        const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 };