SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / drivers / clk / renesas / renesas-cpg-mssr.h

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 2303baa1fd29ed4fdf64bdad00c3ac795a2e4a83..bad393878511c88d6343d28f8a96d9dee61e1e77 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Renesas RCar Gen3 CPG MSSR driver
  *
@@ -7,8 +8,6 @@
  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
  *
  * Copyright (C) 2016 Glider bvba
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
@@ -23,17 +22,13 @@ struct cpg_mssr_info {
        unsigned int                    mstp_table_size;
        const char                      *reset_node;
        const char                      *extalr_node;
+       const char                      *extal_usb_node;
        unsigned int                    mod_clk_base;
        unsigned int                    clk_extal_id;
        unsigned int                    clk_extalr_id;
-};
-
-struct gen3_clk_priv {
-       void __iomem            *base;
-       struct cpg_mssr_info    *info;
-       struct clk              clk_extal;
-       struct clk              clk_extalr;
-       const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+       unsigned int                    clk_extal_usb_id;
+       unsigned int                    pll0_div;
+       const void                      *(*get_pll_config)(const u32 cpg_mode);
 };
 
 /*
@@ -60,6 +55,8 @@ enum clk_types {
        /* Generic */
        CLK_TYPE_IN,            /* External Clock Input */
        CLK_TYPE_FF,            /* Fixed Factor Clock */
+       CLK_TYPE_DIV6P1,        /* DIV6 Clock with 1 parent clock */
+       CLK_TYPE_DIV6_RO,       /* DIV6 Clock read only with extra divisor */
 
        /* Custom definitions start here */
        CLK_TYPE_CUSTOM,
@@ -74,14 +71,10 @@ enum clk_types {
        DEF_TYPE(_name, _id, CLK_TYPE_IN)
 #define DEF_FIXED(_name, _id, _parent, _div, _mult)    \
        DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
-#define DEF_GEN3_SD(_name, _id, _parent, _offset)      \
-       DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset)     \
-       DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
-#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
-                   _div_clean) \
-       DEF_BASE(_name, _id, CLK_TYPE_FF,                       \
-                (_parent_clean), .div = (_div_clean), 1)
+#define DEF_DIV6P1(_name, _id, _parent, _offset)       \
+       DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
+#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)        \
+       DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
 
 /*
  * Definitions of Module Clocks
@@ -100,37 +93,24 @@ struct mssr_mod_clk {
 #define DEF_MOD(_name, _mod, _parent...)       \
        { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
 
-enum rcar_gen3_clk_types {
-       CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
-       CLK_TYPE_GEN3_PLL0,
-       CLK_TYPE_GEN3_PLL1,
-       CLK_TYPE_GEN3_PLL2,
-       CLK_TYPE_GEN3_PLL3,
-       CLK_TYPE_GEN3_PLL4,
-       CLK_TYPE_GEN3_SD,
-       CLK_TYPE_GEN3_RPC,
-       CLK_TYPE_GEN3_R,
-       CLK_TYPE_GEN3_PE,
-       CLK_TYPE_GEN3_Z2,
-};
-
-struct rcar_gen3_cpg_pll_config {
-       unsigned int extal_div;
-       unsigned int pll1_mult;
-       unsigned int pll3_mult;
-};
-
 struct mstp_stop_table {
-       u32     dis;
-       u32     en;
+       u32     sdis;
+       u32     sen;
+       u32     rdis;
+       u32     ren;
 };
 
 #define TSTR0          0x04
 #define TSTR0_STR0     BIT(0)
 
-int gen3_clk_probe(struct udevice *dev);
-int gen3_clk_remove(struct udevice *dev);
-
-extern const struct clk_ops gen3_clk_ops;
+bool renesas_clk_is_mod(struct clk *clk);
+int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
+                       const struct mssr_mod_clk **mssr);
+int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
+                        const struct cpg_core_clk **core);
+int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
+                          struct clk *parent);
+int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
+int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
 
 #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */