Merge git://git.denx.de/u-boot-socfpga

[u-boot] / drivers / clk / rockchip / clk_rk3036.c

diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 28652df72d0444ff1f3764624f2ad4cc2c5cd1df..510a00a3aaf32f0a33f54335c2d6bda87f4eb505 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -40,7 +40,7 @@ enum {
                         #hz "Hz cannot be hit with PLL "\
                         "divisors on line " __stringify(__LINE__));
 
-/* use interge mode*/
+/* use integer mode*/
 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
 
@@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
        assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
               output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
 
-       /* use interger mode */
-       rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+       /* use integer mode */
+       rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
 
        rk_clrsetreg(&pll->con0,
                     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
@@ -235,7 +235,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
        }
 
        src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
-       return DIV_TO_RATE(src_rate, div);
+       return DIV_TO_RATE(src_rate, div) / 2;
 }
 
 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
@@ -247,10 +247,11 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
        debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
 
        /* mmc clock auto divide 2 in internal */
-       src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+       src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 
-       if (src_clk_div > 0x7f) {
-               src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+       if (src_clk_div > 128) {
+               src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div - 1 < 128);
                mux = EMMC_SEL_24M;
        } else {
                mux = EMMC_SEL_GPLL;
@@ -329,11 +330,29 @@ static int rk3036_clk_probe(struct udevice *dev)
 static int rk3036_clk_bind(struct udevice *dev)
 {
        int ret;
+       struct udevice *sys_child;
+       struct sysreset_reg *priv;
 
        /* The reset driver does not have a device node, so bind it here */
-       ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
+       ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+                                &sys_child);
+       if (ret) {
+               debug("Warning: No sysreset driver: ret=%d\n", ret);
+       } else {
+               priv = malloc(sizeof(struct sysreset_reg));
+               priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
+                                                   cru_glb_srst_fst_value);
+               priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
+                                                   cru_glb_srst_snd_value);
+               sys_child->priv = priv;
+       }
+
+#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+       ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
+       ret = rockchip_reset_bind(dev, ret, 9);
        if (ret)
-               debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
+               debug("Warning: software reset driver bind faile\n");
+#endif
 
        return 0;
 }