Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

[u-boot] / drivers / clk / rockchip / clk_rk3288.c

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index f6ef7ecd7a1fc723d46955e81791ec58cb757732..ac53239363c7478bc0d7f86f26f17983437b21ff 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <bitfield.h>
 #include <clk-uclass.h>
 #include <dm.h>
 #include <dt-structs.h>
@@ -111,6 +112,15 @@ enum {
        PERI_ACLK_DIV_SHIFT     = 0,
        PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 
+       /*
+        * CLKSEL24
+        * saradc_div_con:
+        * clk_saradc=24MHz/(saradc_div_con+1)
+        */
+       CLK_SARADC_DIV_CON_SHIFT        = 8,
+       CLK_SARADC_DIV_CON_MASK         = GENMASK(15, 8),
+       CLK_SARADC_DIV_CON_WIDTH        = 8,
+
        SOCSTS_DPLL_LOCK        = 1 << 5,
        SOCSTS_APLL_LOCK        = 1 << 6,
        SOCSTS_CPLL_LOCK        = 1 << 7,
@@ -118,9 +128,6 @@ enum {
        SOCSTS_NPLL_LOCK        = 1 << 9,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _nr, _no) {\
@@ -131,10 +138,8 @@ enum {
 
 /* Keep divisors as low as possible to reduce jitter and power usage */
 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
-#ifdef CONFIG_SPL_BUILD
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
-#endif
 
 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
                         const struct pll_div *div)
@@ -340,9 +345,8 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 
        return 0;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
-#ifdef CONFIG_SPL_BUILD
 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 {
        u32 aclk_div;
@@ -416,7 +420,6 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
                     GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
                     CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 }
-#endif
 
 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 {
@@ -534,10 +537,12 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
        int mux;
 
        debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
-       src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+       /* mmc clock default div 2 internal, need provide double in cru */
+       src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
 
        if (src_clk_div > 0x3f) {
-               src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
+               src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div < 0x40);
                mux = EMMC_PLL_SELECT_24MHZ;
                assert((int)EMMC_PLL_SELECT_24MHZ ==
                       (int)MMC0_PLL_SELECT_24MHZ);
@@ -611,7 +616,8 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
        int src_clk_div;
 
        debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
-       src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+       src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+       assert(src_clk_div < 128);
        switch (periph) {
        case SCLK_SPI0:
                rk_clrsetreg(&cru->cru_clksel_con[25],
@@ -638,6 +644,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
        return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
+static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
+{
+       u32 div, val;
+
+       val = readl(&cru->cru_clksel_con[24]);
+       div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+                              CLK_SARADC_DIV_CON_WIDTH);
+
+       return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
+{
+       int src_clk_div;
+
+       src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+       assert(src_clk_div < 128);
+
+       rk_clrsetreg(&cru->cru_clksel_con[24],
+                    CLK_SARADC_DIV_CON_MASK,
+                    src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+       return rockchip_saradc_get_clk(cru);
+}
+
 static ulong rk3288_clk_get_rate(struct clk *clk)
 {
        struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
@@ -670,6 +701,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
                return gclk_rate;
        case PCLK_PWM:
                return PD_BUS_PCLK_HZ;
+       case SCLK_SARADC:
+               new_rate = rockchip_saradc_get_clk(priv->cru);
+               break;
        default:
                return -ENOENT;
        }
@@ -760,6 +794,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
                new_rate = rate;
                break;
 #endif
+       case SCLK_SARADC:
+               new_rate = rockchip_saradc_set_clk(priv->cru, rate);
+               break;
        default:
                return -ENOENT;
        }
@@ -786,6 +823,7 @@ static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
 static int rk3288_clk_probe(struct udevice *dev)
 {
        struct rk3288_clk_priv *priv = dev_get_priv(dev);
+       bool init_clocks = false;
 
        priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
        if (IS_ERR(priv->grf))
@@ -796,8 +834,24 @@ static int rk3288_clk_probe(struct udevice *dev)
 
        priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
 #endif
-       rkclk_init(priv->cru, priv->grf);
+       init_clocks = true;
 #endif
+       if (!(gd->flags & GD_FLG_RELOC)) {
+               u32 reg;
+
+               /*
+                * Init clocks in U-Boot proper if the NPLL is runnning. This
+                * indicates that a previous boot loader set up the clocks, so
+                * we need to redo it. U-Boot's SPL does not set this clock.
+                */
+               reg = readl(&priv->cru->cru_mode_con);
+               if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
+                               NPLL_MODE_NORMAL)
+                       init_clocks = true;
+       }
+
+       if (init_clocks)
+               rkclk_init(priv->cru, priv->grf);
 
        return 0;
 }
@@ -805,11 +859,22 @@ static int rk3288_clk_probe(struct udevice *dev)
 static int rk3288_clk_bind(struct udevice *dev)
 {
        int ret;
+       struct udevice *sys_child;
+       struct sysreset_reg *priv;
 
        /* The reset driver does not have a device node, so bind it here */
-       ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
-       if (ret)
-               debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
+       ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+                                &sys_child);
+       if (ret) {
+               debug("Warning: No sysreset driver: ret=%d\n", ret);
+       } else {
+               priv = malloc(sizeof(struct sysreset_reg));
+               priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
+                                                   cru_glb_srst_fst_value);
+               priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
+                                                   cru_glb_srst_snd_value);
+               sys_child->priv = priv;
+       }
 
        return 0;
 }