ARM: socfpga: Repair A10 EMAC reset handling

[u-boot] / drivers / ddr / altera / sdram.c

diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 1ed2883d1b8460795117a1d21ff0a3e2188f906f..821060459cf143af860ef749666f71af9f90772c 100644 (file)
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright Altera Corporation (C) 2014-2015
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <common.h>
 #include <errno.h>
@@ -12,8 +11,6 @@
 #include <asm/arch/system_manager.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 struct sdram_prot_rule {
        u32     sdram_start;    /* SDRAM start address */
        u32     sdram_end;      /* SDRAM end address */
@@ -118,7 +115,7 @@ static void sdram_set_rule(struct sdram_prot_rule *prule)
 
        /* Obtain the address bits */
        lo_addr_bits = prule->sdram_start >> 20ULL;
-       hi_addr_bits = prule->sdram_end >> 20ULL;
+       hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 
        debug("sdram set rule start %x, %d\n", lo_addr_bits,
              prule->sdram_start);
@@ -218,6 +215,7 @@ static void sdram_dump_protection_config(void)
              readl(&sdr_ctrl->protport_default));
 
        for (rules = 0; rules < 20; rules++) {
+               rule.rule = rules;
                sdram_get_rule(&rule);
                debug("Rule %d, rules ...\n", rules);
                debug("    sdram start %x\n", rule.sdram_start);
@@ -417,6 +415,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 
        debug("Configuring DRAMODT\n");
        writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+       debug("Configuring EXTRATIME1\n");
+       writel(cfg->extratime1, &sdr_ctrl->extratime1);
 }
 
 /**