menu "Freescale DDR controllers"
depends on SYS_FSL_DDR
+config SYS_NUM_DDR_CTLRS
+ int "Maximum DDR controllers"
+ default 3 if ARCH_LS2080A || \
+ ARCH_T4240
+ default 2 if ARCH_B4860 || \
+ ARCH_BSC9132 || \
+ ARCH_MPC8572 || \
+ ARCH_MPC8641 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T4160
+ default 1
+
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
endchoice
endmenu
+
+config SYS_FSL_ERRATUM_A008378
+ bool
+
+config SYS_FSL_ERRATUM_A008511
+ bool
+
+config SYS_FSL_ERRATUM_A009663
+ bool
+
+config SYS_FSL_ERRATUM_A009801
+ bool
+
+config SYS_FSL_ERRATUM_A009803
+ bool
+
+config SYS_FSL_ERRATUM_A009942
+ bool
+
+config SYS_FSL_ERRATUM_A010165
+ bool
+
+config SYS_FSL_ERRATUM_NMG_DDR120
+ bool
+
+config SYS_FSL_ERRATUM_DDR_115
+ bool
+
+config SYS_FSL_ERRATUM_DDR111_DDR134
+ bool
+
+config SYS_FSL_ERRATUM_DDR_A003
+ bool
+
+config SYS_FSL_ERRATUM_DDR_A003474
+ bool