Merge tag 'xilinx-for-v2018.03' of git://git.denx.de/u-boot-microblaze

[u-boot] / drivers / ddr / fsl / arm_ddr_gen3.c

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 59f2fd661096964a79c4edcc302084c39a7adf80..aaf4dfb1e79514a79a036c2e184a6e224afe6db2 100644 (file)
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -12,6 +12,7 @@
 #include <asm/processor.h>
 #include <fsl_immap.h>
 #include <fsl_ddr.h>
+#include <asm/arch/clock.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -40,17 +41,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        case 0:
                ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
                break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
        case 1:
                ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
        case 2:
                ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
        case 3:
                ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
                break;
@@ -92,7 +93,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
        ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
        ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-       ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
        ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
        ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -105,9 +105,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
        ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
        ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-       ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
-       ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
        ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
        ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
        ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
@@ -128,7 +125,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
        ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-       ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               ddr_out32(&ddr->sdram_cfg_2,
+                         regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+               ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+               /* DRAM VRef will not be trained */
+               ddr_out32(&ddr->ddr_cdr2,
+                         regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+       } else
+#endif
+       {
+               ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+               ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
+               ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+               ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       }
        ddr_out32(&ddr->err_disable, regs->err_disable);
        ddr_out32(&ddr->err_int_en, regs->err_int_en);
        for (i = 0; i < 32; i++) {
@@ -167,8 +181,20 @@ step2:
        udelay(500);
        asm volatile("dsb sy;isb");
 
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               /* enter self-refresh */
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+               temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+               /* do board specific memory setup */
+               board_mem_sleep_setup();
+
+               temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
+       } else
+#endif
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        /* Let the controller go */
-       temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
        ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
        asm volatile("dsb sy;isb");
 
@@ -197,7 +223,7 @@ step2:
        bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
                        >> SDRAM_CFG_DBW_SHIFT);
        timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-               (get_ddr_freq(0) >> 20)) << 1;
+               (get_ddr_freq(ctrl_num) >> 20)) << 1;
        total_gb_size_per_controller >>= 4;     /* shift down to gb size */
        debug("total %d GB\n", total_gb_size_per_controller);
        debug("Need to wait up to %d * 10ms\n", timeout);
@@ -211,4 +237,12 @@ step2:
 
        if (timeout <= 0)
                printf("Waiting for D_INIT timeout. Memory may not work.\n");
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               /* exit self-refresh */
+               temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
+               temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+               ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+       }
+#endif
 }