powerpc: MPC8555: Remove macro CONFIG_MPC8555

[u-boot] / drivers / ddr / fsl / ctrl_regs.c

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9073917914e9630a77d4df47870c248357b0f53d..32b09679e2ec4fa9a24ad88ab03ddf9c4cb59fe8 100644 (file)
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
                | ((add_lat_mclk & 0xf) << 28)
                | ((cpo & 0x1f) << 23)
                | ((wr_lat & 0xf) << 19)
-               | ((wr_lat & 0x10) << 14)
+               | (((wr_lat & 0x10) >> 4) << 18)
                | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
                | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
                | ((cke_pls & 0x7) << 6)
@@ -1831,14 +1831,21 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
        unsigned int clk_adjust;        /* Clock adjust */
        unsigned int ss_en = 0;         /* Source synchronous enable */
 
-#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
        /* Per FSL Application Note: AN2805 */
        ss_en = 1;
 #endif
-       clk_adjust = popts->clk_adjust;
+       if (fsl_ddr_get_version(0) >= 0x40701) {
+               /* clk_adjust in 5-bits on T-series and LS-series */
+               clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+       } else {
+               /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+               clk_adjust = (popts->clk_adjust & 0xF) << 23;
+       }
+
        ddr->ddr_sdram_clk_cntl = (0
                                   | ((ss_en & 0x1) << 31)
-                                  | ((clk_adjust & 0xF) << 23)
+                                  | clk_adjust
                                   );
        debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
@@ -2205,7 +2212,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
                 * Write leveling start time
                 * The value use for the DQS_ADJUST for the first sample
                 * when write leveling is enabled. It probably needs to be
-                * overriden per platform.
+                * overridden per platform.
                 */
                wrlvl_start = 0x8;
                /*