Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / drivers / ddr / fsl / ctrl_regs.c

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index dcf6287f66395aa5b100643c0d46973747edefb0..d9cac2296a20afc431dcefa64bba109cd7e6a250 100644 (file)
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
        unsigned int x32_en = 0;        /* x32 enable */
        unsigned int pchb8 = 0;         /* precharge bit 8 enable */
        unsigned int hse;               /* Global half strength override */
+       unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
        unsigned int mem_halt = 0;      /* memory controller halt */
        unsigned int bi = 0;            /* Bypass initialization */
 
@@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
        ba_intlv_ctl = popts->ba_intlv_ctl;
        hse = popts->half_strength_driver_enable;
 
+       /* set when ddr bus width < 64 */
+       acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
+
        ddr->ddr_sdram_cfg = (0
                        | ((mem_en & 0x1) << 31)
                        | ((sren & 0x1) << 30)
@@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
                        | ((x32_en & 0x1) << 5)
                        | ((pchb8 & 0x1) << 4)
                        | ((hse & 0x1) << 3)
+                       | ((acc_ecc_en & 0x1) << 2)
                        | ((mem_halt & 0x1) << 1)
                        | ((bi & 0x1) << 0)
                        );
@@ -1857,6 +1862,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 
        acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
        wrtord_bg = max(4, picos_to_mclk(7500));
+       if (popts->otf_burst_chop_en)
+               wrtord_bg += 2;
+
        pre_all_rec = 0;
 
        ddr->timing_cfg_8 = (0
@@ -2268,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        if (ip_rev > 0x40400)
                unq_mrs_en = 1;
 
+       if (ip_rev > 0x40700)
+               ddr->debug[18] = popts->cswl_override;
+
        set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
        set_ddr_sdram_mode(ddr, popts, common_dimm,
                                cas_latency, additive_latency, unq_mrs_en);