/*
- * Copyright 2010-2014 Freescale Semiconductor, Inc.
+ * Copyright 2010-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
COMMON_TIMING(trrds_ps),
COMMON_TIMING(trrdl_ps),
COMMON_TIMING(tccdl_ps),
+ COMMON_TIMING(trfc_slr_ps),
#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
DIMM_PARM(data_width),
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
+ DIMM_PARM(package_3ds),
DIMM_PARM(registered_dimm),
DIMM_PARM(mirrored_dimm),
DIMM_PARM(device_width),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(bank_addr_bits),
DIMM_PARM(bank_group_bits),
+ DIMM_PARM_HEX(die_density),
#else
DIMM_PARM(n_banks_per_sdram_device),
#endif
DIMM_PARM(trrds_ps),
DIMM_PARM(trrdl_ps),
DIMM_PARM(tccdl_ps),
+ DIMM_PARM(trfc_slr_ps),
#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(data_width),
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
+ DIMM_PARM(package_3ds),
DIMM_PARM(registered_dimm),
DIMM_PARM(mirrored_dimm),
DIMM_PARM(device_width),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(bank_addr_bits),
DIMM_PARM(bank_group_bits),
+ DIMM_PARM_HEX(die_density),
#else
DIMM_PARM(n_banks_per_sdram_device),
#endif
DIMM_PARM(trrds_ps),
DIMM_PARM(trrdl_ps),
DIMM_PARM(tccdl_ps),
+ DIMM_PARM(trfc_slr_ps),
#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
COMMON_TIMING(trrds_ps),
COMMON_TIMING(trrdl_ps),
COMMON_TIMING(tccdl_ps),
+ COMMON_TIMING(trfc_slr_ps),
#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
CTRL_OPTIONS(mirrored_dimm),
CTRL_OPTIONS(ap_en),
CTRL_OPTIONS(x4_en),
+ CTRL_OPTIONS(package_3ds),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(mirrored_dimm),
CTRL_OPTIONS(ap_en),
CTRL_OPTIONS(x4_en),
+ CTRL_OPTIONS(package_3ds),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),