ARM: mvebu: a38x: sync ddr training code with upstream

[u-boot] / drivers / ddr / marvell / a38x / xor.h

diff --git a/drivers/ddr/marvell/a38x/xor.h b/drivers/ddr/marvell/a38x/xor.h
index 7b1e3161772c20ebbe8e62135795d7a368ec277c..1e0265036934a300efd72553dede20d6d1fb3926 100644 (file)
--- a/drivers/ddr/marvell/a38x/xor.h
+++ b/drivers/ddr/marvell/a38x/xor.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) Marvell International Ltd. and its affiliates
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef _XOR_H
@@ -9,8 +8,6 @@
 
 #define SRAM_BASE              0x40000000
 
-#include "ddr3_hws_hw_training_def.h"
-
 #define MV_XOR_MAX_UNIT                2       /* XOR unit == XOR engine */
 #define MV_XOR_MAX_CHAN                4       /* total channels for all units */
 #define MV_XOR_MAX_CHAN_PER_UNIT 2     /* channels for units */
@@ -88,5 +85,6 @@ int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
 int mv_xor_command_set(u32 chan, enum mv_command command);
 int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
                        int enable);
+int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr);
 
 #endif