ARM: socfpga: Convert callers of cm_write_with_phase for wait_for_bit_le32

[u-boot] / drivers / dma / apbh_dma.c

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 22defcd7d9223be898b18cdc8ae1236a38272671..fea8767d7bae5b65013dc33c3b7506748247f646 100644 (file)
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -14,13 +14,13 @@
 
 #include <common.h>
 #include <malloc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/imx-common/dma.h>
-#include <asm/imx-common/regs-apbh.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/regs-apbh.h>
 
 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
 
@@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel)
 #if defined(CONFIG_MX23)
        uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
        uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
        uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
        uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif