8xxx: Rename dma_xfer() to dmacpy()

[u-boot] / drivers / dma / fsl_dma.c

diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index a9989ee5cb74f036c4c5f65a9120ef6d496477c6..49ea8f105da00b91b41bd59f75db12958aabbacb 100644 (file)
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -27,12 +27,16 @@
 
 #include <config.h>
 #include <common.h>
+#include <asm/io.h>
 #include <asm/fsl_dma.h>
 
+/* Controller can only transfer 2^26 - 1 bytes at a time */
+#define FSL_DMA_MAX_SIZE       (0x3ffffff)
+
 #if defined(CONFIG_MPC85xx)
-volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 #elif defined(CONFIG_MPC86xx)
-volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
+ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 #else
 #error "Freescale DMA engine not supported on your processor"
 #endif
@@ -48,14 +52,15 @@ static void dma_sync(void)
 
 static uint dma_check(void) {
        volatile fsl_dma_t *dma = &dma_base->dma[0];
-       volatile uint status = dma->sr;
+       uint status;
 
        /* While the channel is busy, spin */
-       while (status & 4)
-               status = dma->sr;
+       do {
+               status = in_be32(&dma->sr);
+       } while (status & FSL_DMA_SR_CB);
 
        /* clear MR[CS] channel start bit */
-       dma->mr &= 1;
+       out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS);
        dma_sync();
 
        if (status != 0)
@@ -67,26 +72,41 @@ static uint dma_check(void) {
 void dma_init(void) {
        volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-       dma->satr = 0x00040000;
-       dma->datr = 0x00040000;
-       dma->sr = 0xffffffff; /* clear any errors */
+       out_be32(&dma->satr, FSL_DMA_SATR_SREAD_NO_SNOOP);
+       out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_NO_SNOOP);
+       out_be32(&dma->sr, 0xffffffff); /* clear any errors */
        dma_sync();
 }
 
-int dma_xfer(void *dest, uint count, void *src) {
+int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
        volatile fsl_dma_t *dma = &dma_base->dma[0];
+       uint xfer_size;
 
-       dma->dar = (uint) dest;
-       dma->sar = (uint) src;
-       dma->bcr = count;
+       while (count) {
+               xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
 
-       /* Disable bandwidth control, use direct transfer mode */
-       dma->mr = 0xf000004;
-       dma_sync();
+               out_be32(&dma->dar, (uint) dest);
+               out_be32(&dma->sar, (uint) src);
+               out_be32(&dma->bcr, xfer_size);
 
-       /* Start the transfer */
-       dma->mr = 0xf000005;
-       dma_sync();
+               /* Disable bandwidth control, use direct transfer mode */
+               out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT);
+               dma_sync();
+
+               /* Start the transfer */
+               out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS |
+                               FSL_DMA_MR_CTM_DIRECT |
+                               FSL_DMA_MR_CS);
+
+               count -= xfer_size;
+               src += xfer_size;
+               dest += xfer_size;
+
+               dma_sync();
+
+               if (dma_check())
+                       return -1;
+       }
 
-       return dma_check();
+       return 0;
 }