mtd: nand: mxs_nand: use structure for BCH geometry

[u-boot] / drivers / fpga / ACEX1K.c

diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index 06b4247d87e729ad657b7293f9f9f9d245e06962..5afd42a97b6cb7e0c7c89f48d1a66380a166ecd9 100644 (file)
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -1,31 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2003
  * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
  *
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
  */
 
 #include <common.h>            /* core U-Boot definitions */
+#include <console.h>
 #include <ACEX1K.h>            /* ACEX device family */
 
 /* Define FPGA_DEBUG to get debug printf's */
@@ -48,13 +31,13 @@
 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10          /* 100 ms */
 #endif
 
-static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
-static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
-/* static int ACEX1K_ps_info( Altera_desc *desc ); */
+static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
+static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
+/* static int ACEX1K_ps_info(Altera_desc *desc); */
 
 /* ------------------------------------------------------------------------- */
 /* ACEX1K Generic Implementation */
-int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
+int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
 
@@ -74,7 +57,7 @@ int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
        return ret_val;
 }
 
-int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
+int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
 
@@ -103,7 +86,7 @@ int ACEX1K_info( Altera_desc *desc )
 /* ------------------------------------------------------------------------- */
 /* ACEX1K Passive Serial Generic Implementation                                  */
 
-static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;        /* assume the worst */
        Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
@@ -140,7 +123,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
                }
 
                /* Establish the initial state */
-               (*fn->config) (TRUE, TRUE, cookie);     /* Assert nCONFIG */
+               (*fn->config) (true, true, cookie);     /* Assert nCONFIG */
 
                udelay(2);              /* T_cfg > 2us  */
 
@@ -152,7 +135,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
                        return FPGA_FAIL;
                }
 
-               (*fn->config) (FALSE, TRUE, cookie);    /* Deassert nCONFIG */
+               (*fn->config) (false, true, cookie);    /* Deassert nCONFIG */
                udelay(2);              /* T_cf2st1 < 4us       */
 
                /* Wait for nSTATUS to be released (i.e. deasserted) */
@@ -192,13 +175,13 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
                        i = 8;
                        do {
                                /* Deassert the clock */
-                               (*fn->clk) (FALSE, TRUE, cookie);
+                               (*fn->clk) (false, true, cookie);
                                CONFIG_FPGA_DELAY ();
                                /* Write data */
-                               (*fn->data) ( (val & 0x01), TRUE, cookie);
+                               (*fn->data) ((val & 0x01), true, cookie);
                                CONFIG_FPGA_DELAY ();
                                /* Assert the clock */
-                               (*fn->clk) (TRUE, TRUE, cookie);
+                               (*fn->clk) (true, true, cookie);
                                CONFIG_FPGA_DELAY ();
                                val >>= 1;
                                i --;
@@ -232,9 +215,9 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
 
        for (i = 0; i < 12; i++) {
                CONFIG_FPGA_DELAY ();
-               (*fn->clk) (TRUE, TRUE, cookie);        /* Assert the clock pin */
+               (*fn->clk) (true, true, cookie);        /* Assert the clock pin */
                CONFIG_FPGA_DELAY ();
-               (*fn->clk) (FALSE, TRUE, cookie);       /* Deassert the clock pin */
+               (*fn->clk) (false, true, cookie);       /* Deassert the clock pin */
        }
 
        ret_val = FPGA_SUCCESS;
@@ -256,7 +239,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
        return ret_val;
 }
 
-static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
 {
        /* Readback is only available through the Slave Parallel and         */
        /* boundary-scan interfaces.                                         */