arm: socfpga: Fix with the correct polling on bit is set

[u-boot] / drivers / fpga / socfpga_arria10.c

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a00995c33054cdbaaa9d64c9a1c99346be..685e8e271a0342d7c51f059c6e38685098b02b95 100644 (file)
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -62,8 +62,7 @@ int is_fpgamgr_user_mode(void)
 
 static int wait_for_user_mode(void)
 {
-       return wait_for_bit(__func__,
-               &fpga_manager_base->imgcfg_stat,
+       return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
                ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
                1, FPGA_TIMEOUT_MSEC, false);
 }
@@ -112,22 +111,20 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
        unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
                                ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 
-       /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
-        * timeout at 1000ms
+       /*
+        * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+        * de-asserted, timeout at 1000ms
         */
-       return wait_for_bit(__func__,
-                           &fpga_manager_base->imgcfg_stat,
-                           mask,
-                           false, FPGA_TIMEOUT_MSEC, false);
+       return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
+                                true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
 {
        /* Poll until f2s to specific value, timeout at 1000ms */
-       return wait_for_bit(__func__,
-                           &fpga_manager_base->imgcfg_stat,
-                           ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
-                           value, FPGA_TIMEOUT_MSEC, false);
+       return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+               ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+               value, FPGA_TIMEOUT_MSEC, false);
 }
 
 /* set CD ratio */