davinci_emac: compilation fix, phy is array now

[u-boot] / drivers / fpga / spartan3.c

diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 0fe30410a6f93c090e9ee0e8f60fab6e22bfe66b..9207391249a60d0530ae56702cd0b2652c686172 100644 (file)
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -53,17 +53,17 @@
 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
 #endif
 
-static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
+static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
 
-static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
-static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
+static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int Spartan3_ss_info(Xilinx_desc *desc); */
 
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Generic Implementation */
-int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
 
@@ -86,7 +86,7 @@ int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
        return ret_val;
 }
 
-int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
 
@@ -118,7 +118,7 @@ int Spartan3_info( Xilinx_desc *desc )
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */
 
-static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;        /* assume the worst */
        Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
@@ -272,7 +272,7 @@ static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
        return ret_val;
 }
 
-static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;        /* assume the worst */
        Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
@@ -320,7 +320,7 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
 
 /* ------------------------------------------------------------------------- */
 
-static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;        /* assume the worst */
        Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
@@ -366,6 +366,8 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
                        CONFIG_FPGA_DELAY ();
                        if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
                                puts ("** Timeout waiting for INIT to start.\n");
+                               if (*fn->abort)
+                                       (*fn->abort) (cookie);
                                return FPGA_FAIL;
                        }
                } while (!(*fn->init) (cookie));
@@ -380,39 +382,47 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
                        CONFIG_FPGA_DELAY ();
                        if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {    /* check the time */
                                puts ("** Timeout waiting for INIT to clear.\n");
+                               if (*fn->abort)
+                                       (*fn->abort) (cookie);
                                return FPGA_FAIL;
                        }
                } while ((*fn->init) (cookie));
 
                /* Load the data */
-               while (bytecount < bsize) {
-
-                       /* Xilinx detects an error if INIT goes low (active)
-                          while DONE is low (inactive) */
-                       if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
-                               puts ("** CRC error during FPGA load.\n");
-                               return (FPGA_FAIL);
-                       }
-                       val = data [bytecount ++];
-                       i = 8;
-                       do {
-                               /* Deassert the clock */
-                               (*fn->clk) (FALSE, TRUE, cookie);
-                               CONFIG_FPGA_DELAY ();
-                               /* Write data */
-                               (*fn->wr) ((val & 0x80), TRUE, cookie);
-                               CONFIG_FPGA_DELAY ();
-                               /* Assert the clock */
-                               (*fn->clk) (TRUE, TRUE, cookie);
-                               CONFIG_FPGA_DELAY ();
-                               val <<= 1;
-                               i --;
-                       } while (i > 0);
+               if(*fn->bwr)
+                       (*fn->bwr) (data, bsize, TRUE, cookie);
+               else {
+                       while (bytecount < bsize) {
+
+                               /* Xilinx detects an error if INIT goes low (active)
+                                  while DONE is low (inactive) */
+                               if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+                                       puts ("** CRC error during FPGA load.\n");
+                                       if (*fn->abort)
+                                               (*fn->abort) (cookie);
+                                       return (FPGA_FAIL);
+                               }
+                               val = data [bytecount ++];
+                               i = 8;
+                               do {
+                                       /* Deassert the clock */
+                                       (*fn->clk) (FALSE, TRUE, cookie);
+                                       CONFIG_FPGA_DELAY ();
+                                       /* Write data */
+                                       (*fn->wr) ((val & 0x80), TRUE, cookie);
+                                       CONFIG_FPGA_DELAY ();
+                                       /* Assert the clock */
+                                       (*fn->clk) (TRUE, TRUE, cookie);
+                                       CONFIG_FPGA_DELAY ();
+                                       val <<= 1;
+                                       i --;
+                               } while (i > 0);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-                       if (bytecount % (bsize / 40) == 0)
-                               putc ('.');             /* let them know we are alive */
+                               if (bytecount % (bsize / 40) == 0)
+                                       putc ('.');             /* let them know we are alive */
 #endif
+                       }
                }
 
                CONFIG_FPGA_DELAY ();
@@ -465,7 +475,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
        return ret_val;
 }
 
-static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
+static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 {
        /* Readback is only available through the Slave Parallel and         */
        /* boundary-scan interfaces.                                         */