mtd: nand: mxs_nand: use structure for BCH geometry

[u-boot] / drivers / fpga / zynqpl.c

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 2ff716c25228f513fe09fdbc5346caeeed3ff8d2..fd37d18c7f474944348b4f9c8c484f7d386ba449 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012-2013, Xilinx, Michal Simek
  *
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -17,6 +16,7 @@
 #include <asm/arch/sys_proto.h>
 
 #define DEVCFG_CTRL_PCFG_PROG_B                0x40000000
+#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK        0x00001000
 #define DEVCFG_ISR_FATAL_ERROR_MASK    0x00740040
 #define DEVCFG_ISR_ERROR_FLAGS_MASK    0x00340840
 #define DEVCFG_ISR_RX_FIFO_OV          0x00040000
@@ -205,9 +205,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
                /* Setting PCFG_PROG_B signal to high */
                control = readl(&devcfg_base->ctrl);
                writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
+
+               /*
+                * Delay is required if AES efuse is selected as
+                * key source.
+                */
+               if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+                       mdelay(5);
+
                /* Setting PCFG_PROG_B signal to low */
                writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
 
+               /*
+                * Delay is required if AES efuse is selected as
+                * key source.
+                */
+               if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
+                       mdelay(5);
+
                /* Polling the PCAP_INIT status for Reset */
                ts = get_timer(0);
                while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {