dm: core: Add ofnode function to read a 64-bit int

[u-boot] / drivers / gpio / dwapb_gpio.c

diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 471e18aeaa0b3c54091a100214dab6ab735ff69c..a118f58b226a010a2a7c9b49a3eab2036697cb2a 100644 (file)
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2015 Marek Vasut <marex@denx.de>
  *
  * DesignWare APB GPIO driver
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -19,8 +18,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define GPIO_SWPORTA_DR                0x00
-#define GPIO_SWPORTA_DDR       0x04
+#define GPIO_SWPORT_DR(p)      (0x00 + (p) * 0xc)
+#define GPIO_SWPORT_DDR(p)     (0x04 + (p) * 0xc)
 #define GPIO_INTEN             0x30
 #define GPIO_INTMASK           0x34
 #define GPIO_INTTYPE_LEVEL     0x38
@@ -28,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_INTSTATUS         0x40
 #define GPIO_PORTA_DEBOUNCE    0x48
 #define GPIO_PORTA_EOI         0x4c
-#define GPIO_EXT_PORTA         0x50
+#define GPIO_EXT_PORT(p)       (0x50 + (p) * 4)
 
 struct gpio_dwapb_platdata {
        const char      *name;
@@ -41,7 +40,7 @@ static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
 {
        struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
 
-       clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
+       clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
        return 0;
 }
 
@@ -50,12 +49,12 @@ static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
 {
        struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
 
-       setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
+       setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
 
        if (val)
-               setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+               setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
        else
-               clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+               clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
 
        return 0;
 }
@@ -63,7 +62,7 @@ static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
 static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
 {
        struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
-       return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin));
+       return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin));
 }
 
 
@@ -72,9 +71,9 @@ static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
        struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
 
        if (val)
-               setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+               setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
        else
-               clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+               clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
 
        return 0;
 }
@@ -112,13 +111,13 @@ static int gpio_dwapb_bind(struct udevice *dev)
        if (plat)
                return 0;
 
-       base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+       base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
        if (base == FDT_ADDR_T_NONE) {
                debug("Can't get the GPIO register base address\n");
                return -ENXIO;
        }
 
-       for (node = fdt_first_subnode(blob, dev->of_offset);
+       for (node = fdt_first_subnode(blob, dev_of_offset(dev));
             node > 0;
             node = fdt_next_subnode(blob, node)) {
                if (!fdtdec_get_bool(blob, node, "gpio-controller"))
@@ -142,7 +141,7 @@ static int gpio_dwapb_bind(struct udevice *dev)
                if (ret)
                        goto err;
 
-               subdev->of_offset = node;
+               dev_set_of_offset(subdev, node);
                bank++;
        }