serial/serial_arc: set registers address during compilation

[u-boot] / drivers / gpio / intel_ich6_gpio.c

diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b095d17f5745c982c24c7acf69bcdf6ef0dbde93..7720cc3dadfbc1d32a4f2a298243e66e7d438cf4 100644 (file)
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -34,69 +34,21 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/pci.h>
-#ifdef CONFIG_X86_RESET_VECTOR
-#include <asm/arch/pch.h>
-#define SUPPORT_GPIO_SETUP
-#endif
 
 #define GPIO_PER_BANK  32
 
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
 struct ich6_bank_priv {
        /* These are I/O addresses */
-       uint32_t use_sel;
-       uint32_t io_sel;
-       uint32_t lvl;
+       uint16_t use_sel;
+       uint16_t io_sel;
+       uint16_t lvl;
 };
 
-#ifdef SUPPORT_GPIO_SETUP
-static void setup_pch_gpios(const struct pch_gpio_map *gpio)
-{
-       u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
-
-       /* GPIO Set 1 */
-       if (gpio->set1.level)
-               outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
-       if (gpio->set1.mode)
-               outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
-       if (gpio->set1.direction)
-               outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
-       if (gpio->set1.reset)
-               outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
-       if (gpio->set1.invert)
-               outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
-       if (gpio->set1.blink)
-               outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
-
-       /* GPIO Set 2 */
-       if (gpio->set2.level)
-               outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
-       if (gpio->set2.mode)
-               outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
-       if (gpio->set2.direction)
-               outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
-       if (gpio->set2.reset)
-               outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
-
-       /* GPIO Set 3 */
-       if (gpio->set3.level)
-               outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
-       if (gpio->set3.mode)
-               outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
-       if (gpio->set3.direction)
-               outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
-       if (gpio->set3.reset)
-               outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
-}
-
 /* TODO: Move this to device tree, or platform data */
 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
 {
        gd->arch.gpio_map = map;
 }
-#endif /* SUPPORT_GPIO_SETUP */
 
 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 {
@@ -105,7 +57,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
        u8 tmpbyte;
        u16 tmpword;
        u32 tmplong;
-       u32 gpiobase;
+       u16 gpiobase;
        int offset;
 
        /* Where should it be? */
@@ -164,11 +116,15 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
        /*
         * GPIOBASE moved to its current offset with ICH6, but prior to
         * that it was unused (or undocumented). Check that it looks
-        * okay: not all ones or zeros, and mapped to I/O space (bit 0).
+        * okay: not all ones or zeros.
+        *
+        * Note we don't need check bit0 here, because the Tunnel Creek
+        * GPIO base address register bit0 is reserved (read returns 0),
+        * while on the Ivybridge the bit0 is used to indicate it is an
+        * I/O space.
         */
        tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
-       if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
-           !(tmplong & 0x00000001)) {
+       if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
                debug("%s: unexpected GPIOBASE value\n", __func__);
                return -ENODEV;
        }
@@ -179,7 +135,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
         * at the offset that we just read. Bit 0 indicates that it's
         * an I/O address, not a memory address, so mask that off.
         */
-       gpiobase = tmplong & 0xfffffffe;
+       gpiobase = tmplong & 0xfffe;
        offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
        if (offset == -1) {
                debug("%s: Invalid register offset %d\n", __func__, offset);
@@ -198,12 +154,11 @@ static int ich6_gpio_probe(struct udevice *dev)
        struct gpio_dev_priv *uc_priv = dev->uclass_priv;
        struct ich6_bank_priv *bank = dev_get_priv(dev);
 
-#ifdef SUPPORT_GPIO_SETUP
        if (gd->arch.gpio_map) {
-               setup_pch_gpios(gd->arch.gpio_map);
+               setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
                gd->arch.gpio_map = NULL;
        }
-#endif
+
        uc_priv->gpio_count = GPIO_PER_BANK;
        uc_priv->bank_name = plat->bank_name;
        bank->use_sel = plat->base_addr;
@@ -251,6 +206,8 @@ static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
        struct ich6_bank_priv *bank = dev_get_priv(dev);
        u32 tmplong;
 
+       gpio_set_value(offset, value);
+
        tmplong = inl(bank->io_sel);
        tmplong &= ~(1UL << offset);
        outl(bank->io_sel, tmplong);