avoid duplicating the logic in the TPS65090 regulator driver for
enabling/disabling an LDO.
+config I2C_SET_DEFAULT_BUS_NUM
+ bool "Set default I2C bus number"
+ depends on DM_I2C
+ help
+ Set default number of I2C bus to be accessed. This option provides
+ behaviour similar to old (i.e. pre DM) I2C bus driver.
+
+config I2C_DEFAULT_BUS_NUMBER
+ hex "I2C default bus number"
+ depends on I2C_SET_DEFAULT_BUS_NUM
+ default 0x0
+ help
+ Number of default I2C bus to use
+
config DM_I2C_GPIO
bool "Enable Driver Model for software emulated I2C bus driver"
depends on DM_I2C && DM_GPIO
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_AT91
+ bool "Atmel I2C driver"
+ depends on DM_I2C && ARCH_AT91
+ help
+ Add support for the Atmel I2C driver. A serious problem is that there
+ is no documented way to issue repeated START conditions for more than
+ two messages, as needed to support combined I2C messages. Use the
+ i2c-gpio driver unless your system can cope with this limitation.
+ Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
+
config SYS_I2C_FSL
bool "Freescale I2C bus driver"
depends on DM_I2C
enable status register. This config option can be enabled in such
cases.
+config SYS_I2C_ASPEED
+ bool "Aspeed I2C Controller"
+ depends on DM_I2C && ARCH_ASPEED
+ help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
the I2C API meaning that any I2C operations will immediately fail
for now.
+config SYS_I2C_IMX_LPI2C
+ bool "NXP i.MX LPI2C driver"
+ help
+ Add support for the NXP i.MX LPI2C driver.
+
+config SYS_I2C_MESON
+ bool "Amlogic Meson I2C driver"
+ depends on DM_I2C && ARCH_MESON
+ help
+ Add support for the I2C controller available in Amlogic Meson
+ SoCs. The controller supports programmable bus speed including
+ standard (100kbits/s) and fast (400kbit/s) speed and allows the
+ software to define a flexible format of the bit streams. It has an
+ internal buffer holding up to 8 bytes for transfers and supports
+ both 7-bit and 10-bit addresses.
+
+config SYS_I2C_MXC
+ bool "NXP i.MX I2C driver"
+ depends on MX6
+ help
+ Add support for the NXP i.MX I2C driver. This supports upto for bus
+ channels and operating on standard mode upto 100 kbits/s and fast
+ mode upto 400 kbits/s.
+
+config SYS_I2C_OMAP24XX
+ bool "TI OMAP2+ I2C driver"
+ depends on ARCH_OMAP2PLUS
+ help
+ Add support for the OMAP2+ I2C driver.
+
+if SYS_I2C_OMAP24XX
+config SYS_OMAP24_I2C_SLAVE
+ int "I2C Slave addr channel 0"
+ default 1
+ help
+ OMAP24xx I2C Slave address channel 0
+
+config SYS_OMAP24_I2C_SPEED
+ int "I2C Slave channel 0 speed"
+ default 100000
+ help
+ OMAP24xx Slave speed channel 0
+endif
+
+config SYS_I2C_RCAR_IIC
+ bool "Renesas RCar Gen3 IIC driver"
+ depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
+ help
+ Support for Renesas RCar Gen3 IIC controller.
+
config SYS_I2C_ROCKCHIP
bool "Rockchip I2C driver"
depends on DM_I2C
help
Enable I2C support for sandbox. This is an emulation of a real I2C
bus. Devices can be attached to the bus using the device tree
- which specifies the driver to use. As an example, see this device
- tree fragment from sandbox.dts. It shows that the I2C bus has a
- single EEPROM at address 0x2c (7-bit address) which is emulated by
- the driver for "sandbox,i2c-eeprom", which is in
- drivers/misc/i2c_eeprom_emul.c.
-
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- compatible = "sandbox,i2c";
- clock-frequency = <400000>;
- eeprom@2c {
- reg = <0x2c>;
- compatible = "i2c-eeprom";
- emul {
- compatible = "sandbox,i2c-eeprom";
- sandbox,filename = "i2c.bin";
- sandbox,size = <128>;
- };
- };
- };
+ which specifies the driver to use. See sandbox.dts as an example.
+config SYS_I2C_S3C24X0
+ bool "Samsung I2C driver"
+ depends on ARCH_EXYNOS4 && DM_I2C
+ help
+ Support for Samsung I2C controller as Samsung SoCs.
+
+config SYS_I2C_STM32F7
+ bool "STMicroelectronics STM32F7 I2C support"
+ depends on (STM32F7 || STM32H7) && DM_I2C
+ help
+ Enable this option to add support for STM32 I2C controller
+ introduced with STM32F7/H7 SoCs. This I2C controller supports :
+ _ Slave and master modes
+ _ Multimaster capability
+ _ Standard-mode (up to 100 kHz)
+ _ Fast-mode (up to 400 kHz)
+ _ Fast-mode Plus (up to 1 MHz)
+ _ 7-bit and 10-bit addressing mode
+ _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
+ _ All 7-bit addresses acknowledge mode
+ _ General call
+ _ Programmable setup and hold times
+ _ Easy to use event management
+ _ Optional clock stretching
+ _ Software reset
config SYS_I2C_UNIPHIER
bool "UniPhier I2C driver"
by the BPMP, and can only be accessed by the main CPU via IPC
requests to the BPMP. This driver covers the latter case.
+config SYS_I2C_BUS_MAX
+ int "Max I2C busses"
+ depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
+ default 2 if TI816X
+ default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
+ default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
+ default 5 if OMAP54XX
+ help
+ Define the maximum number of available I2C buses.
+
+config SYS_I2C_ZYNQ
+ bool "Xilinx I2C driver"
+ depends on ARCH_ZYNQMP || ARCH_ZYNQ
+ help
+ Support for Xilinx I2C controller.
+
+config SYS_I2C_IHS
+ bool "gdsys IHS I2C driver"
+ depends on DM_I2C
+ help
+ Support for gdsys IHS I2C driver on FPGA bus.
+
source "drivers/i2c/muxes/Kconfig"
endmenu
projects / u-boot / blobdiff