]> git.sur5r.net Git - u-boot/blobdiff - drivers/i2c/fsl_i2c.c
Merge git://git.denx.de/u-boot-dm
[u-boot] / drivers / i2c / fsl_i2c.c
index 291ad946dba19a8b358b4be6fe3c12be018d73a1..ff7f25a0ef7cdf2ce46cecc7954e654bc0d0d853 100644 (file)
@@ -38,7 +38,7 @@
  * generic value.
  */
 #ifndef CONFIG_I2C_TIMEOUT
-#define CONFIG_I2C_TIMEOUT     10000
+#define CONFIG_I2C_TIMEOUT     100000
 #endif
 
 #define I2C_READ_BIT  1
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct fsl_i2c *i2c_dev[2] = {
+static const struct fsl_i2c *i2c_dev[4] = {
        (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
-       (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
+       (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
+#endif
+#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
+       (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
+#endif
+#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
+       (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
 #endif
 };
 
@@ -121,7 +127,7 @@ static const struct {
 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
        unsigned int i2c_clk, unsigned int speed)
 {
-       unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
+       unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
 
        /*
         * We want to choose an FDR/DFSR that generates an I2C bus speed that
@@ -423,18 +429,45 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
        struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
        int i = -1; /* signal error */
        u8 *a = (u8*)&addr;
+       int len = alen * -1;
 
        if (i2c_wait4bus(adap) < 0)
                return -1;
 
-       if ((!length || alen > 0)
-           && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
-           && __i2c_write(adap, &a[4 - alen], alen) == alen)
-               i = 0; /* No error so far */
+       /* To handle the need of I2C devices that require to write few bytes
+        * (more than 4 bytes of address as in the case of else part)
+        * of data before reading, Negative equivalent of length(bytes to write)
+        * is passed, but used the +ve part of len for writing data
+        */
+       if (alen < 0) {
+               /* Generate a START and send the Address and
+                * the Tx Bytes to the slave.
+                * "START: Address: Write bytes data[len]"
+                * IF part supports writing any number of bytes in contrast
+                * to the else part, which supports writing address offset
+                * of upto 4 bytes only.
+                * bytes that need to be written are passed in
+                * "data", which will eventually keep the data READ,
+                * after writing the len bytes out of it
+                */
+               if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
+                       i = __i2c_write(adap, data, len);
+
+               if (i != len)
+                       return -1;
 
-       if (length &&
-           i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
-               i = __i2c_read(adap, data, length);
+               if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
+                       i = __i2c_read(adap, data, length);
+       } else {
+               if ((!length || alen > 0) &&
+                   i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0  &&
+                   __i2c_write(adap, &a[4 - alen], alen) == alen)
+                       i = 0; /* No error so far */
+
+               if (length &&
+                   i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
+                       i = __i2c_read(adap, data, length);
+       }
 
        writeb(I2C_CR_MEN, &device->cr);
 
@@ -512,3 +545,15 @@ U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
                         CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
                         1)
 #endif
+#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+                        fsl_i2c_write, fsl_i2c_set_bus_speed,
+                        CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
+                        2)
+#endif
+#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
+U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
+                        fsl_i2c_write, fsl_i2c_set_bus_speed,
+                        CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
+                        3)
+#endif