+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
*
* This file is based on: drivers/i2c/zynq_i2c.c,
* with added driver-model support and code cleanup.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/errno.h>
-#include <dm/device.h>
#include <dm/root.h>
#include <i2c.h>
#include <fdtdec.h>
#include <mapmem.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <wait_bit.h>
/* i2c register set */
struct cdns_i2c_regs {
#define CDNS_I2C_FIFO_DEPTH 16
#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
#ifdef DEBUG
return 0;
}
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
- uint chip_flags)
-{
- struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
- struct cdns_i2c_regs *regs = i2c_bus->regs;
-
- /* Attempt to read a byte */
- setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
- CDNS_I2C_CONTROL_RW);
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
- writel(0xFF, ®s->interrupt_status);
- writel(chip_addr, ®s->address);
- writel(1, ®s->transfer_size);
-
- return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
- CDNS_I2C_INTERRUPT_NACK) &
- CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
-}
-
static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
u32 len)
{
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
+ /* Set the controller in Master transmit mode and clear FIFO */
setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
-
-
clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
+ /* Check message size against FIFO depth, and set hold bus bit
+ * if it is greater than FIFO depth
+ */
+ if (len > CDNS_I2C_FIFO_DEPTH)
+ setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
+
+ /* Clear the interrupts in status register */
writel(0xFF, ®s->interrupt_status);
+
writel(addr, ®s->address);
while (len--) {
return 0;
}
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+ return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
{
- u32 status;
- u32 i = 0;
u8 *cur_data = data;
-
- /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+ int curr_recv_count;
+ int updatetx, hold_quirk;
/* Check the hardware can handle the requested bytes */
- if ((len < 0))
+ if ((recv_count < 0))
return -EINVAL;
+ curr_recv_count = recv_count;
+
+ /* Check for the message size against the FIFO depth */
+ if (recv_count > CDNS_I2C_FIFO_DEPTH)
+ setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
+ if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+ curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+ writel(curr_recv_count, ®s->transfer_size);
+ } else {
+ writel(recv_count, ®s->transfer_size);
+ }
+
/* Start reading data */
writel(addr, ®s->address);
- writel(len, ®s->transfer_size);
-
- /* Wait for data */
- do {
- status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
- CDNS_I2C_INTERRUPT_DATA);
- if (!status) {
- /* Release the bus */
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
+
+ updatetx = recv_count > curr_recv_count;
+
+ hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+ while (recv_count) {
+ while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
+ if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+ !i2c_bus->hold_flag) {
+ clrbits_le32(®s->control,
+ CDNS_I2C_CONTROL_HOLD);
+ }
+ *(cur_data)++ = readl(®s->data);
+ recv_count--;
+ curr_recv_count--;
+
+ if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+ break;
}
- debug("Read %d bytes\n",
- len - readl(®s->transfer_size));
- for (; i < len - readl(®s->transfer_size); i++)
- *(cur_data++) = readl(®s->data);
- } while (readl(®s->transfer_size) != 0);
- /* All done... release the bus */
- if (!i2c_bus->hold_flag)
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
-#ifdef DEBUG
- cdns_i2c_debug_status(regs);
-#endif
+ if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
+ /* wait while fifo is full */
+ while (readl(®s->transfer_size) !=
+ (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
+ ;
+ /*
+ * Check number of bytes to be received against maximum
+ * transfer size and update register accordingly.
+ */
+ if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
+ CDNS_I2C_TRANSFER_SIZE) {
+ writel(CDNS_I2C_TRANSFER_SIZE,
+ ®s->transfer_size);
+ curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
+ CDNS_I2C_FIFO_DEPTH;
+ } else {
+ writel(recv_count - CDNS_I2C_FIFO_DEPTH,
+ ®s->transfer_size);
+ curr_recv_count = recv_count;
+ }
+ } else if (recv_count && !hold_quirk && !curr_recv_count) {
+ writel(addr, ®s->address);
+ if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+ writel(CDNS_I2C_TRANSFER_SIZE,
+ ®s->transfer_size);
+ curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+ } else {
+ writel(recv_count, ®s->transfer_size);
+ curr_recv_count = recv_count;
+ }
+ }
+ }
+
+ /* Wait for the address and data to be sent */
+ if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
+ return -ETIMEDOUT;
+
return 0;
}
struct cdns_i2c_platform_data *pdata =
(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
- i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
+ i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
if (!i2c_bus->regs)
return -ENOMEM;
static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
- .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
};
projects / u-boot / blobdiff