+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
*
* This file is based on: drivers/i2c/zynq_i2c.c,
* with added driver-model support and code cleanup.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
#include <linux/types.h>
#include <linux/io.h>
-#include <asm/errno.h>
-#include <dm/device.h>
+#include <linux/errno.h>
#include <dm/root.h>
#include <i2c.h>
#include <fdtdec.h>
#include <mapmem.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <wait_bit.h>
/* i2c register set */
struct cdns_i2c_regs {
#define CDNS_I2C_FIFO_DEPTH 16
#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
+#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
+
+#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
#ifdef DEBUG
static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
struct i2c_cdns_bus {
int id;
+ unsigned int input_freq;
struct cdns_i2c_regs __iomem *regs; /* register base */
-};
-
-
-/** cdns_i2c_probe() - Probe method
- * @dev: udevice pointer
- *
- * DM callback called when device is probed
- */
-static int cdns_i2c_probe(struct udevice *dev)
-{
- struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
- bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
- if (!bus->regs)
- return -ENOMEM;
-
- /* TODO: Calculate dividers based on CPU_CLK_1X */
- /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
- writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
- (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
-
- /* Enable master mode, ack, and 7-bit addressing */
- setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
- CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
-
- debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
- return 0;
-}
-static int cdns_i2c_remove(struct udevice *dev)
-{
- struct i2c_cdns_bus *bus = dev_get_priv(dev);
-
- debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs);
-
- unmap_sysmem(bus->regs);
+ int hold_flag;
+ u32 quirks;
+};
- return 0;
-}
+struct cdns_i2c_platform_data {
+ u32 quirks;
+};
/* Wait for an interrupt */
static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
int timeout, int_status;
for (timeout = 0; timeout < 100; timeout++) {
- udelay(100);
int_status = readl(&cdns_i2c->interrupt_status);
if (int_status & mask)
break;
+ udelay(100);
}
/* Clear interrupt status flags */
return int_status & mask;
}
-static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+#define CDNS_I2C_DIVA_MAX 4
+#define CDNS_I2C_DIVB_MAX 64
+
+static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
+ unsigned int *a, unsigned int *b)
{
- if (speed != 100000) {
- printf("%s, failed to set clock speed to %u\n", __func__,
- speed);
+ unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
+ unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
+ unsigned int last_error, current_error;
+
+ /* calculate (divisor_a+1) x (divisor_b+1) */
+ temp = input_clk / (22 * fscl);
+
+ /*
+ * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
+ * the fscl input is out of range. Return error.
+ */
+ if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
return -EINVAL;
+
+ last_error = -1;
+ for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
+ div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
+
+ if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
+ continue;
+ div_b--;
+
+ actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
+
+ if (actual_fscl > fscl)
+ continue;
+
+ current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
+ (fscl - actual_fscl));
+
+ if (last_error > current_error) {
+ calc_div_a = div_a;
+ calc_div_b = div_b;
+ best_fscl = actual_fscl;
+ last_error = current_error;
+ }
}
+ *a = calc_div_a;
+ *b = calc_div_b;
+ *f = best_fscl;
+
return 0;
}
-/* Probe to see if a chip is present. */
-static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
- uint chip_flags)
+static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
{
- struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
- struct cdns_i2c_regs *regs = i2c_bus->regs;
+ struct i2c_cdns_bus *bus = dev_get_priv(dev);
+ u32 div_a = 0, div_b = 0;
+ unsigned long speed_p = speed;
+ int ret = 0;
- /* Attempt to read a byte */
- setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
- CDNS_I2C_CONTROL_RW);
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
- writel(0xFF, ®s->interrupt_status);
- writel(chip_addr, ®s->address);
- writel(1, ®s->transfer_size);
+ if (speed > 400000) {
+ debug("%s, failed to set clock speed to %u\n", __func__,
+ speed);
+ return -EINVAL;
+ }
+
+ ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
+ if (ret)
+ return ret;
+
+ debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
+ __func__, div_a, div_b, bus->input_freq, speed, speed_p);
+
+ writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
+ (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
+
+ /* Enable master mode, ack, and 7-bit addressing */
+ setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
+ CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
- return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
- CDNS_I2C_INTERRUPT_NACK) &
- CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
+ return 0;
}
static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len, bool next_is_read)
+ u32 len)
{
u8 *cur_data = data;
-
struct cdns_i2c_regs *regs = i2c_bus->regs;
- setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
- CDNS_I2C_CONTROL_HOLD);
-
- /* if next is a read, we need to clear HOLD, doesn't work */
- if (next_is_read)
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
-
+ /* Set the controller in Master transmit mode and clear FIFO */
+ setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
+ /* Check message size against FIFO depth, and set hold bus bit
+ * if it is greater than FIFO depth
+ */
+ if (len > CDNS_I2C_FIFO_DEPTH)
+ setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
+
+ /* Clear the interrupts in status register */
writel(0xFF, ®s->interrupt_status);
+
writel(addr, ®s->address);
while (len--) {
}
/* All done... release the bus */
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
+ if (!i2c_bus->hold_flag)
+ clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
+
/* Wait for the address and data to be sent */
if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
return -ETIMEDOUT;
return 0;
}
+static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
+{
+ return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
+}
+
static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
- u32 len)
+ u32 recv_count)
{
- u32 status;
- u32 i = 0;
u8 *cur_data = data;
-
- /* TODO: Fix this */
struct cdns_i2c_regs *regs = i2c_bus->regs;
+ int curr_recv_count;
+ int updatetx, hold_quirk;
/* Check the hardware can handle the requested bytes */
- if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
+ if ((recv_count < 0))
return -EINVAL;
+ curr_recv_count = recv_count;
+
+ /* Check for the message size against the FIFO depth */
+ if (recv_count > CDNS_I2C_FIFO_DEPTH)
+ setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
+
setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
CDNS_I2C_CONTROL_RW);
+ if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+ curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+ writel(curr_recv_count, ®s->transfer_size);
+ } else {
+ writel(recv_count, ®s->transfer_size);
+ }
+
/* Start reading data */
writel(addr, ®s->address);
- writel(len, ®s->transfer_size);
-
- /* Wait for data */
- do {
- status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
- CDNS_I2C_INTERRUPT_DATA);
- if (!status) {
- /* Release the bus */
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
- return -ETIMEDOUT;
+
+ updatetx = recv_count > curr_recv_count;
+
+ hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
+
+ while (recv_count) {
+ while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
+ if (recv_count < CDNS_I2C_FIFO_DEPTH &&
+ !i2c_bus->hold_flag) {
+ clrbits_le32(®s->control,
+ CDNS_I2C_CONTROL_HOLD);
+ }
+ *(cur_data)++ = readl(®s->data);
+ recv_count--;
+ curr_recv_count--;
+
+ if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
+ break;
}
- debug("Read %d bytes\n",
- len - readl(®s->transfer_size));
- for (; i < len - readl(®s->transfer_size); i++)
- *(cur_data++) = readl(®s->data);
- } while (readl(®s->transfer_size) != 0);
- /* All done... release the bus */
- clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
-#ifdef DEBUG
- cdns_i2c_debug_status(regs);
-#endif
+ if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
+ /* wait while fifo is full */
+ while (readl(®s->transfer_size) !=
+ (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
+ ;
+ /*
+ * Check number of bytes to be received against maximum
+ * transfer size and update register accordingly.
+ */
+ if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
+ CDNS_I2C_TRANSFER_SIZE) {
+ writel(CDNS_I2C_TRANSFER_SIZE,
+ ®s->transfer_size);
+ curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
+ CDNS_I2C_FIFO_DEPTH;
+ } else {
+ writel(recv_count - CDNS_I2C_FIFO_DEPTH,
+ ®s->transfer_size);
+ curr_recv_count = recv_count;
+ }
+ } else if (recv_count && !hold_quirk && !curr_recv_count) {
+ writel(addr, ®s->address);
+ if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
+ writel(CDNS_I2C_TRANSFER_SIZE,
+ ®s->transfer_size);
+ curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
+ } else {
+ writel(recv_count, ®s->transfer_size);
+ curr_recv_count = recv_count;
+ }
+ }
+ }
+
+ /* Wait for the address and data to be sent */
+ if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
+ return -ETIMEDOUT;
+
return 0;
}
int nmsgs)
{
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
- int ret;
+ int ret, count;
+ bool hold_quirk;
+
+ hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
+
+ if (nmsgs > 1) {
+ /*
+ * This controller does not give completion interrupt after a
+ * master receive message if HOLD bit is set (repeated start),
+ * resulting in SW timeout. Hence, if a receive message is
+ * followed by any other message, an error is returned
+ * indicating that this sequence is not supported.
+ */
+ for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
+ if (msg[count].flags & I2C_M_RD) {
+ printf("Can't do repeated start after a receive message\n");
+ return -EOPNOTSUPP;
+ }
+ }
+
+ i2c_bus->hold_flag = 1;
+ setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
+ } else {
+ i2c_bus->hold_flag = 0;
+ }
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
- bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
-
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
if (msg->flags & I2C_M_RD) {
ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
msg->len);
} else {
ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
- msg->len, next_is_read);
+ msg->len);
}
if (ret) {
debug("i2c_write: error sending\n");
return 0;
}
+static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
+ struct cdns_i2c_platform_data *pdata =
+ (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
+
+ i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
+ if (!i2c_bus->regs)
+ return -ENOMEM;
+
+ if (pdata)
+ i2c_bus->quirks = pdata->quirks;
+
+ i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
+
+ return 0;
+}
+
static const struct dm_i2c_ops cdns_i2c_ops = {
.xfer = cdns_i2c_xfer,
- .probe_chip = cdns_i2c_probe_chip,
.set_bus_speed = cdns_i2c_set_bus_speed,
};
+static const struct cdns_i2c_platform_data r1p10_i2c_def = {
+ .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
+};
+
static const struct udevice_id cdns_i2c_of_match[] = {
- { .compatible = "cdns,i2c-r1p10" },
+ { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
+ { .compatible = "cdns,i2c-r1p14" },
{ /* end of table */ }
};
.name = "i2c-cdns",
.id = UCLASS_I2C,
.of_match = cdns_i2c_of_match,
- .probe = cdns_i2c_probe,
- .remove = cdns_i2c_remove,
+ .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
.ops = &cdns_i2c_ops,
};
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