* as they seem to have the same I2C controller inside.
* The different address mapping is handled by the s3c24xx.h files below.
*/
-
#include <common.h>
+#include <errno.h>
+#include <dm.h>
#include <fdtdec.h>
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include <asm/arch/clk.h>
#include <i2c.h>
#include "s3c24x0_i2c.h"
-#ifdef CONFIG_HARD_I2C
-
#define I2C_WRITE 0
#define I2C_READ 1
#define I2C_START_STOP 0x20 /* START / STOP */
#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
-#define I2C_TIMEOUT_MS 1000 /* 1 second */
+#define I2C_TIMEOUT_MS 10 /* 10 ms */
-#define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */
+#define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
/* To support VCMA9 boards and other who dont define max_i2c_num */
#define CONFIG_MAX_I2C_NUM 1
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* For SPL boot some boards need i2c before SDRAM is initialised so force
* variables to live in SRAM
*/
-static unsigned int g_current_bus __attribute__((section(".data")));
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
__attribute__((section(".data")));
+#endif
+
+enum exynos_i2c_type {
+ EXYNOS_I2C_STD,
+ EXYNOS_I2C_HS,
+};
+#ifdef CONFIG_SYS_I2C
/**
* Get a pointer to the given bus index
*
debug("Undefined bus: %d\n", bus_idx);
return NULL;
}
+#endif
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
static int GetI2CSDA(void)
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
return (readl(&gpio->gpedat) & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
{
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
writel((readl(&gpio->gpedat) & ~0x4000) |
(x & 1) << 14, &gpio->gpedat);
#endif
return I2C_NOK_TOUT;
}
-static void ReadWriteByte(struct s3c24x0_i2c *i2c)
+static void read_write_byte(struct s3c24x0_i2c *i2c)
{
- writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
+ clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
}
-static struct s3c24x0_i2c *get_base_i2c(void)
+#ifdef CONFIG_SYS_I2C
+static struct s3c24x0_i2c *get_base_i2c(int bus)
{
#ifdef CONFIG_EXYNOS4
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS4_I2C_SPACING
- * g_current_bus));
+ * bus));
return i2c;
#elif defined CONFIG_EXYNOS5
struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+ (EXYNOS5_I2C_SPACING
- * g_current_bus));
+ * bus));
return i2c;
#else
return s3c24x0_get_base_i2c();
#endif
}
+#endif
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
}
-#ifdef CONFIG_I2C_MULTI_BUS
static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
{
struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
unsigned int i = 0, utemp0 = 0, utemp1 = 0;
unsigned int t_ftl_cycle;
-#if defined CONFIG_EXYNOS5
+#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
clkin = get_i2c_clk();
+#else
+ clkin = get_PCLK();
#endif
/* FPCLK / FI2C =
* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
return 0;
}
}
- return -1;
+ return -EINVAL;
}
-#endif
static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
{
hsi2c_ch_init(i2c_bus);
}
-/*
- * MULTI BUS I2C support
- */
-
-#ifdef CONFIG_I2C_MULTI_BUS
-int i2c_set_bus_num(unsigned int bus)
-{
- struct s3c24x0_i2c_bus *i2c_bus;
-
- i2c_bus = get_bus(bus);
- if (!i2c_bus)
- return -1;
- g_current_bus = bus;
-
- if (i2c_bus->is_highspeed) {
- if (hsi2c_get_clk_details(i2c_bus))
- return -1;
- hsi2c_ch_init(i2c_bus);
- } else {
- i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
- CONFIG_SYS_I2C_SLAVE);
- }
-
- return 0;
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return g_current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveadd)
+#ifdef CONFIG_SYS_I2C
+static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct s3c24x0_i2c *i2c;
+ struct s3c24x0_i2c_bus *bus;
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#endif
ulong start_time = get_timer(0);
- /* By default i2c channel 0 is the current bus */
- g_current_bus = 0;
- i2c = get_base_i2c();
+ i2c = get_base_i2c(adap->hwadapnr);
+ bus = &i2c_bus[adap->hwadapnr];
+ if (!bus)
+ return;
/*
* In case the previous transfer is still going, wait to give it a
int i;
if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
ulong old_gpecon = readl(&gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
/* bus still busy probably by (most) previously interrupted
transfer */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
&gpio->gpecon);
udelay(1000);
/* restore pin functions */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
writel(old_gpecon, &gpio->gpecon);
#endif
#ifdef CONFIG_S3C2400
#endif
}
#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
+
i2c_ch_init(i2c, speed, slaveadd);
+
+ bus->active = true;
+ bus->regs = i2c;
}
+#endif /* CONFIG_SYS_I2C */
/*
* Poll the appropriate bit of the fifo status register until the interface is
return rv;
}
+#ifdef CONFIG_SYS_I2C
+static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+#else
+static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+#endif
+{
+ struct s3c24x0_i2c_bus *i2c_bus;
+
+#ifdef CONFIG_SYS_I2C
+ i2c_bus = get_bus(adap->hwadapnr);
+ if (!i2c_bus)
+ return -EFAULT;
+#else
+ i2c_bus = dev_get_priv(dev);
+#endif
+ i2c_bus->clock_frequency = speed;
+
+ if (i2c_bus->is_highspeed) {
+ if (hsi2c_get_clk_details(i2c_bus))
+ return -EFAULT;
+ hsi2c_ch_init(i2c_bus);
+ } else {
+ i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
+ }
+
+ return 0;
+}
+
/*
* cmd_type is 0 for write, 1 for read.
*
if (addr && addr_len) {
while ((i < addr_len) && (result == I2C_OK)) {
writel(addr[i++], &i2c->iicds);
- ReadWriteByte(i2c);
+ read_write_byte(i2c);
result = WaitForXfer(i2c);
}
i = 0;
case I2C_WRITE:
while ((i < data_len) && (result == I2C_OK)) {
writel(data[i++], &i2c->iicds);
- ReadWriteByte(i2c);
+ read_write_byte(i2c);
result = WaitForXfer(i2c);
}
break;
/* Generate a re-START. */
writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
&i2c->iicstat);
- ReadWriteByte(i2c);
+ read_write_byte(i2c);
result = WaitForXfer(i2c);
if (result != I2C_OK)
writel(readl(&i2c->iiccon)
& ~I2CCON_ACKGEN,
&i2c->iiccon);
- ReadWriteByte(i2c);
+ read_write_byte(i2c);
result = WaitForXfer(i2c);
data[i++] = readl(&i2c->iicds);
}
bailout:
/* Send STOP. */
writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
- ReadWriteByte(i2c);
+ read_write_byte(i2c);
return result;
}
-int i2c_probe(uchar chip)
+#ifdef CONFIG_SYS_I2C
+static int s3c24x0_i2c_probe(struct i2c_adapter *adap, uchar chip)
+#else
+static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
+#endif
{
struct s3c24x0_i2c_bus *i2c_bus;
uchar buf[1];
int ret;
- i2c_bus = get_bus(g_current_bus);
+#ifdef CONFIG_SYS_I2C
+ i2c_bus = get_bus(adap->hwadapnr);
if (!i2c_bus)
- return -1;
+ return -EFAULT;
+#else
+ i2c_bus = dev_get_priv(dev);
+#endif
buf[0] = 0;
/*
I2C_READ, chip << 1, 0, 0, buf, 1);
}
-
return ret != I2C_OK;
}
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+#ifdef CONFIG_SYS_I2C
+static int s3c24x0_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
struct s3c24x0_i2c_bus *i2c_bus;
uchar xaddr[4];
int ret;
+ i2c_bus = get_bus(adap->hwadapnr);
+ if (!i2c_bus)
+ return -EFAULT;
+
if (alen > 4) {
debug("I2C read: addr len %d not supported\n", alen);
- return 1;
+ return -EADDRNOTAVAIL;
}
if (alen > 0) {
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- i2c_bus = get_bus(g_current_bus);
- if (!i2c_bus)
- return -1;
-
if (i2c_bus->is_highspeed)
ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen],
alen, buffer, len);
if (i2c_bus->is_highspeed)
exynos5_i2c_reset(i2c_bus);
debug("I2c read failed %d\n", ret);
- return 1;
+ return -EIO;
}
return 0;
}
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int s3c24x0_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
{
struct s3c24x0_i2c_bus *i2c_bus;
uchar xaddr[4];
int ret;
+ i2c_bus = get_bus(adap->hwadapnr);
+ if (!i2c_bus)
+ return -EFAULT;
+
if (alen > 4) {
debug("I2C write: addr len %d not supported\n", alen);
- return 1;
+ return -EINVAL;
}
if (alen > 0) {
chip |= ((addr >> (alen * 8)) &
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- i2c_bus = get_bus(g_current_bus);
- if (!i2c_bus)
- return -1;
-
if (i2c_bus->is_highspeed)
ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen],
alen, buffer, len, true);
}
}
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
static void process_nodes(const void *blob, int node_list[], int count,
int is_highspeed)
{
struct s3c24x0_i2c_bus *bus;
- int i;
+ int i, flags;
for (i = 0; i < count; i++) {
int node = node_list[i];
bus->active = true;
bus->is_highspeed = is_highspeed;
- if (is_highspeed)
+ if (is_highspeed) {
+ flags = PINMUX_FLAG_HS_MODE;
bus->hsregs = (struct exynos5_hsi2c *)
fdtdec_get_addr(blob, node, "reg");
- else
+ } else {
+ flags = 0;
bus->regs = (struct s3c24x0_i2c *)
fdtdec_get_addr(blob, node, "reg");
+ }
bus->id = pinmux_decode_periph_id(blob, node);
bus->clock_frequency = fdtdec_get_int(blob, node,
- "clock-frequency",
- CONFIG_SYS_I2C_SPEED);
+ "clock-frequency",
+ CONFIG_SYS_I2C_S3C24X0_SPEED);
bus->node = node;
bus->bus_num = i;
- exynos_pinmux_config(bus->id, 0);
+ exynos_pinmux_config(bus->id, flags);
/* Mark position as used */
node_list[i] = -1;
COMPAT_SAMSUNG_EXYNOS5_I2C, node_list,
CONFIG_MAX_I2C_NUM);
process_nodes(blob, node_list, count, 1);
-
}
int i2c_get_bus_num_fdt(int node)
}
debug("%s: Can't find any matched I2C bus\n", __func__);
- return -1;
+ return -EINVAL;
}
-#ifdef CONFIG_I2C_MULTI_BUS
int i2c_reset_port_fdt(const void *blob, int node)
{
struct s3c24x0_i2c_bus *i2c_bus;
bus = i2c_get_bus_num_fdt(node);
if (bus < 0) {
debug("could not get bus for node %d\n", node);
- return -1;
+ return bus;
}
i2c_bus = get_bus(bus);
if (!i2c_bus) {
- debug("get_bus() failed for node node %d\n", node);
- return -1;
+ debug("get_bus() failed for node %d\n", node);
+ return -EFAULT;
}
if (i2c_bus->is_highspeed) {
if (hsi2c_get_clk_details(i2c_bus))
- return -1;
+ return -EINVAL;
hsi2c_ch_init(i2c_bus);
} else {
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
- CONFIG_SYS_I2C_SLAVE);
+ CONFIG_SYS_I2C_S3C24X0_SLAVE);
}
return 0;
}
+#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+
+#ifdef CONFIG_EXYNOS5
+static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+ /* This will override the speed selected in the fdt for that port */
+ debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
+ if (i2c_set_bus_speed(speed))
+ error("i2c_init: failed to init bus for speed = %d", speed);
+}
+#endif /* CONFIG_EXYNOS5 */
+
+/*
+ * Register s3c24x0 i2c adapters
+ */
+#if defined(CONFIG_EXYNOS5420)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+U_BOOT_I2C_ADAP_COMPLETE(i2c09, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
+U_BOOT_I2C_ADAP_COMPLETE(i2c10, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
+#elif defined(CONFIG_EXYNOS5250)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, exynos_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+U_BOOT_I2C_ADAP_COMPLETE(i2c09, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 9)
+U_BOOT_I2C_ADAP_COMPLETE(s3c10, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 10)
+#elif defined(CONFIG_EXYNOS4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c00, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
+U_BOOT_I2C_ADAP_COMPLETE(i2c01, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 1)
+U_BOOT_I2C_ADAP_COMPLETE(i2c02, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 2)
+U_BOOT_I2C_ADAP_COMPLETE(i2c03, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 3)
+U_BOOT_I2C_ADAP_COMPLETE(i2c04, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 4)
+U_BOOT_I2C_ADAP_COMPLETE(i2c05, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 5)
+U_BOOT_I2C_ADAP_COMPLETE(i2c06, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 6)
+U_BOOT_I2C_ADAP_COMPLETE(i2c07, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 7)
+U_BOOT_I2C_ADAP_COMPLETE(i2c08, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 8)
+#else
+U_BOOT_I2C_ADAP_COMPLETE(s3c0, s3c24x0_i2c_init, s3c24x0_i2c_probe,
+ s3c24x0_i2c_read, s3c24x0_i2c_write,
+ s3c24x0_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_S3C24X0_SPEED,
+ CONFIG_SYS_I2C_S3C24X0_SLAVE, 0)
#endif
-#endif
+#endif /* CONFIG_SYS_I2C */
+
+#ifdef CONFIG_DM_I2C
+static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+ struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
+ int ret;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ if (msg->flags & I2C_M_RD) {
+ ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
+ msg->len);
+ } else {
+ ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
+ msg->len, true);
+ }
+ if (ret) {
+ exynos5_i2c_reset(i2c_bus);
+ return -EREMOTEIO;
+ }
+ }
+
+ return 0;
+}
+
+static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
+ int seq)
+{
+ struct s3c24x0_i2c *i2c = i2c_bus->regs;
+ bool is_read = msg->flags & I2C_M_RD;
+ uint status;
+ uint addr;
+ int ret, i;
+
+ if (!seq)
+ setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
+
+ /* Get the slave chip address going */
+ addr = msg->addr << 1;
+ writel(addr, &i2c->iicds);
+ status = I2C_TXRX_ENA | I2C_START_STOP;
+ if (is_read)
+ status |= I2C_MODE_MR;
+ else
+ status |= I2C_MODE_MT;
+ writel(status, &i2c->iicstat);
+ if (seq)
+ read_write_byte(i2c);
+
+ /* Wait for chip address to transmit */
+ ret = WaitForXfer(i2c);
+ if (ret)
+ goto err;
+
+ if (is_read) {
+ for (i = 0; !ret && i < msg->len; i++) {
+ /* disable ACK for final READ */
+ if (i == msg->len - 1)
+ clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
+ read_write_byte(i2c);
+ ret = WaitForXfer(i2c);
+ msg->buf[i] = readl(&i2c->iicds);
+ }
+ if (ret == I2C_NACK)
+ ret = I2C_OK; /* Normal terminated read */
+ } else {
+ for (i = 0; !ret && i < msg->len; i++) {
+ writel(msg->buf[i], &i2c->iicds);
+ read_write_byte(i2c);
+ ret = WaitForXfer(i2c);
+ }
+ }
+
+err:
+ return ret;
+}
+
+static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+ struct s3c24x0_i2c *i2c = i2c_bus->regs;
+ ulong start_time;
+ int ret, i;
+
+ start_time = get_timer(0);
+ while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
+ if (get_timer(start_time) > I2C_TIMEOUT_MS) {
+ debug("Timeout\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ for (ret = 0, i = 0; !ret && i < nmsgs; i++)
+ ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
+
+ /* Send STOP */
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
+ read_write_byte(i2c);
+
+ return ret ? -EREMOTEIO : 0;
+}
-#endif /* CONFIG_HARD_I2C */
+static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
+ int node, flags;
+
+ i2c_bus->is_highspeed = dev_get_driver_data(dev);
+ node = dev->of_offset;
+
+ if (i2c_bus->is_highspeed) {
+ flags = PINMUX_FLAG_HS_MODE;
+ i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
+ } else {
+ flags = 0;
+ i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
+ }
+
+ i2c_bus->id = pinmux_decode_periph_id(blob, node);
+
+ i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
+ "clock-frequency", 100000);
+ i2c_bus->node = node;
+ i2c_bus->bus_num = dev->seq;
+
+ exynos_pinmux_config(i2c_bus->id, flags);
+
+ i2c_bus->active = true;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops s3c_i2c_ops = {
+ .xfer = s3c24x0_i2c_xfer,
+ .probe_chip = s3c24x0_i2c_probe,
+ .set_bus_speed = s3c24x0_i2c_set_bus_speed,
+};
+
+static const struct udevice_id s3c_i2c_ids[] = {
+ { .compatible = "samsung,s3c2440-i2c", .data = EXYNOS_I2C_STD },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_s3c) = {
+ .name = "i2c_s3c",
+ .id = UCLASS_I2C,
+ .of_match = s3c_i2c_ids,
+ .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
+ .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+ .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
+ .ops = &s3c_i2c_ops,
+};
+
+/*
+ * TODO(sjg@chromium.org): Move this to a separate file when everything uses
+ * driver model
+ */
+static const struct dm_i2c_ops exynos_hs_i2c_ops = {
+ .xfer = exynos_hs_i2c_xfer,
+ .probe_chip = s3c24x0_i2c_probe,
+ .set_bus_speed = s3c24x0_i2c_set_bus_speed,
+};
+
+static const struct udevice_id exynos_hs_i2c_ids[] = {
+ { .compatible = "samsung,exynos5-hsi2c", .data = EXYNOS_I2C_HS },
+ { }
+};
+
+U_BOOT_DRIVER(hs_i2c) = {
+ .name = "i2c_s3c_hs",
+ .id = UCLASS_I2C,
+ .of_match = exynos_hs_i2c_ids,
+ .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
+ .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
+ .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
+ .ops = &exynos_hs_i2c_ops,
+};
+#endif /* CONFIG_DM_I2C */
projects / u-boot / blobdiff