net: mvneta: zero Tx descriptors on init

[u-boot] / drivers / i2c / s3c24x0_i2c.h

diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
index a56d749dec0adcc3c767552a4d3487211e751dfb..ec8f1acaef5416165a31c421ecbc33e4b0cfb744 100644 (file)
--- a/drivers/i2c/s3c24x0_i2c.h
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -1,23 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Samsung Electronics
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #ifndef _S3C24X0_I2C_H
@@ -31,10 +14,70 @@ struct s3c24x0_i2c {
        u32     iiclc;
 };
 
+struct exynos5_hsi2c {
+       u32     usi_ctl;
+       u32     usi_fifo_ctl;
+       u32     usi_trailing_ctl;
+       u32     usi_clk_ctl;
+       u32     usi_clk_slot;
+       u32     spi_ctl;
+       u32     uart_ctl;
+       u32     res1;
+       u32     usi_int_en;
+       u32     usi_int_stat;
+       u32     usi_modem_stat;
+       u32     usi_error_stat;
+       u32     usi_fifo_stat;
+       u32     usi_txdata;
+       u32     usi_rxdata;
+       u32     res2;
+       u32     usi_conf;
+       u32     usi_auto_conf;
+       u32     usi_timeout;
+       u32     usi_manual_cmd;
+       u32     usi_trans_status;
+       u32     usi_timing_hs1;
+       u32     usi_timing_hs2;
+       u32     usi_timing_hs3;
+       u32     usi_timing_fs1;
+       u32     usi_timing_fs2;
+       u32     usi_timing_fs3;
+       u32     usi_timing_sla;
+       u32     i2c_addr;
+};
+
 struct s3c24x0_i2c_bus {
+       bool active;    /* port is active and available */
        int node;       /* device tree node */
        int bus_num;    /* i2c bus number */
        struct s3c24x0_i2c *regs;
+       struct exynos5_hsi2c *hsregs;
+       int is_highspeed;       /* High speed type, rather than I2C */
+       unsigned clock_frequency;
        int id;
+       unsigned clk_cycle;
+       unsigned clk_div;
 };
+
+#define        I2C_WRITE       0
+#define I2C_READ       1
+
+#define I2C_OK         0
+#define I2C_NOK                1
+#define I2C_NACK       2
+#define I2C_NOK_LA     3       /* Lost arbitration */
+#define I2C_NOK_TOUT   4       /* time out */
+
+/* S3C I2C Controller bits */
+#define I2CSTAT_BSY    0x20    /* Busy bit */
+#define I2CSTAT_NACK   0x01    /* Nack bit */
+#define I2CCON_ACKGEN  0x80    /* Acknowledge generation */
+#define I2CCON_IRPND   0x10    /* Interrupt pending bit */
+#define I2C_MODE_MT    0xC0    /* Master Transmit Mode */
+#define I2C_MODE_MR    0x80    /* Master Receive Mode */
+#define I2C_START_STOP 0x20    /* START / STOP */
+#define I2C_TXRX_ENA   0x10    /* I2C Tx/Rx enable */
+
+#define I2C_TIMEOUT_MS 10              /* 10 ms */
+
 #endif /* _S3C24X0_I2C_H */