ppc4xx: Kilauea: Fix SDRAM init in NAND booting version

[u-boot] / drivers / i2c / soft_i2c.c

diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 0a9feb67c7c5b8cd42c7fee834935547b41605b9..59883a58f674e96d696e98de6df2e9d13b630d1f 100644 (file)
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #ifdef CONFIG_MPC8260                  /* only valid for MPC8260 */
 #include <ioports.h>
+#include <asm/io.h>
 #endif
 #ifdef CONFIG_AT91RM9200               /* need this for the at91rm9200 */
 #include <asm/io.h>
@@ -39,6 +40,9 @@
 #ifdef CONFIG_LPC2292
 #include <asm/arch/hardware.h>
 #endif
+#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
+#include <asm/io.h>
+#endif
 #include <i2c.h>
 
 /* #define     DEBUG_I2C       */
@@ -47,14 +51,12 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-
 /*-----------------------------------------------------------------------
  * Definitions
  */
 
 #define RETRIES                0
 
-
 #define I2C_ACK                0               /* PD_SDA level to ack a byte */
 #define I2C_NOACK      1               /* PD_SDA level to noack a byte */
 
@@ -69,13 +71,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #if defined(CONFIG_I2C_MULTI_BUS)
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
 #endif /* CONFIG_I2C_MULTI_BUS */
 
 /*-----------------------------------------------------------------------
  * Local functions
  */
-#if !defined(CFG_I2C_INIT_BOARD)
+#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
 static void  send_reset        (void);
 #endif
 static void  send_start        (void);
@@ -84,7 +86,7 @@ static void  send_ack (int);
 static int   write_byte        (uchar byte);
 static uchar read_byte (int);
 
-#if !defined(CFG_I2C_INIT_BOARD)
+#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
 /*-----------------------------------------------------------------------
  * Send a reset sequence consisting of 9 clocks with the data signal high
  * to clock any confused device back into an idle state.  Also send a
@@ -150,7 +152,6 @@ static void send_stop(void)
        I2C_TRISTATE;
 }
 
-
 /*-----------------------------------------------------------------------
  * ack should be I2C_ACK or I2C_NOACK
  */
@@ -170,7 +171,6 @@ static void send_ack(int ack)
        I2C_DELAY;
 }
 
-
 /*-----------------------------------------------------------------------
  * Send 8 bits and look for an acknowledgement.
  */
@@ -224,7 +224,7 @@ unsigned int i2c_get_bus_num(void)
 int i2c_set_bus_num(unsigned int bus)
 {
 #if defined(CONFIG_I2C_MUX)
-       if (bus < CFG_MAX_I2C_BUS) {
+       if (bus < CONFIG_SYS_MAX_I2C_BUS) {
                i2c_bus_num = bus;
        } else {
                int     ret;
@@ -236,26 +236,12 @@ int i2c_set_bus_num(unsigned int bus)
                        return ret;
        }
 #else
-       if (bus >= CFG_MAX_I2C_BUS)
+       if (bus >= CONFIG_SYS_MAX_I2C_BUS)
                return -1;
        i2c_bus_num = bus;
 #endif
        return 0;
 }
-
-/* TODO: add 100/400k switching */
-unsigned int i2c_get_bus_speed(void)
-{
-       return CFG_I2C_SPEED;
-}
-
-int i2c_set_bus_speed(unsigned int speed)
-{
-       if (speed != CFG_I2C_SPEED)
-               return -1;
-
-       return 0;
-}
 #endif
 
 /*-----------------------------------------------------------------------
@@ -297,7 +283,7 @@ static uchar read_byte(int ack)
  */
 void i2c_init (int speed, int slaveaddr)
 {
-#if defined(CFG_I2C_INIT_BOARD)
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
        /* call board specific i2c bus reset routine before accessing the   */
        /* environment, which might be in a chip on that bus. For details   */
        /* about this problem see doc/I2C_Edge_Conditions.                  */
@@ -342,7 +328,7 @@ int  i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
        PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
                chip, addr, alen, buffer, len);
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
        /*
         * EEPROM chips that implement "address overflow" are ones
         * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -354,7 +340,7 @@ int  i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
         * still be one byte because the extra address bits are
         * hidden in the chip address.
         */
-       chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+       chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 
        PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
                chip, addr);
@@ -381,8 +367,18 @@ int  i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
                        }
                        shift -= 8;
                }
-               send_stop();    /* reportedly some chips need a full stop */
+
+               /* Some I2C chips need a stop/start sequence here,
+                * other chips don't work with a full stop and need
+                * only a start.  Default behaviour is to send the
+                * stop/start sequence.
+                */
+#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
                send_start();
+#else
+               send_stop();
+               send_start();
+#endif
        }
        /*
         * Send the chip address again, this time for a read cycle.
@@ -430,23 +426,3 @@ int  i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
        send_stop();
        return(failures);
 }
-
-/*-----------------------------------------------------------------------
- * Read a register
- */
-uchar i2c_reg_read(uchar i2c_addr, uchar reg)
-{
-       uchar buf;
-
-       i2c_read(i2c_addr, reg, 1, &buf, 1);
-
-       return(buf);
-}
-
-/*-----------------------------------------------------------------------
- * Write a register
- */
-void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
-{
-       i2c_write(i2c_addr, reg, 1, &val, 1);
-}