]> git.sur5r.net Git - u-boot/blobdiff - drivers/i2c/soft_i2c.c
ppc4xx: Kilauea: Fix SDRAM init in NAND booting version
[u-boot] / drivers / i2c / soft_i2c.c
index ebe60e23380e662422b38c0c6e2df4f5aaeae9dc..59883a58f674e96d696e98de6df2e9d13b630d1f 100644 (file)
@@ -40,7 +40,7 @@
 #ifdef CONFIG_LPC2292
 #include <asm/arch/hardware.h>
 #endif
-#ifdef CONFIG_MPC866                   /* only valid for MPC866 */
+#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
 #include <asm/io.h>
 #endif
 #include <i2c.h>
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-
 /*-----------------------------------------------------------------------
  * Definitions
  */
 
 #define RETRIES                0
 
-
 #define I2C_ACK                0               /* PD_SDA level to ack a byte */
 #define I2C_NOACK      1               /* PD_SDA level to noack a byte */
 
@@ -73,7 +71,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #if defined(CONFIG_I2C_MULTI_BUS)
-static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
 #endif /* CONFIG_I2C_MULTI_BUS */
 
 /*-----------------------------------------------------------------------
@@ -154,7 +152,6 @@ static void send_stop(void)
        I2C_TRISTATE;
 }
 
-
 /*-----------------------------------------------------------------------
  * ack should be I2C_ACK or I2C_NOACK
  */
@@ -174,7 +171,6 @@ static void send_ack(int ack)
        I2C_DELAY;
 }
 
-
 /*-----------------------------------------------------------------------
  * Send 8 bits and look for an acknowledgement.
  */
@@ -246,20 +242,6 @@ int i2c_set_bus_num(unsigned int bus)
 #endif
        return 0;
 }
-
-/* TODO: add 100/400k switching */
-unsigned int i2c_get_bus_speed(void)
-{
-       return CONFIG_SYS_I2C_SPEED;
-}
-
-int i2c_set_bus_speed(unsigned int speed)
-{
-       if (speed != CONFIG_SYS_I2C_SPEED)
-               return -1;
-
-       return 0;
-}
 #endif
 
 /*-----------------------------------------------------------------------
@@ -385,8 +367,18 @@ int  i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
                        }
                        shift -= 8;
                }
-               send_stop();    /* reportedly some chips need a full stop */
+
+               /* Some I2C chips need a stop/start sequence here,
+                * other chips don't work with a full stop and need
+                * only a start.  Default behaviour is to send the
+                * stop/start sequence.
+                */
+#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
+               send_start();
+#else
+               send_stop();
                send_start();
+#endif
        }
        /*
         * Send the chip address again, this time for a read cycle.
@@ -434,23 +426,3 @@ int  i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
        send_stop();
        return(failures);
 }
-
-/*-----------------------------------------------------------------------
- * Read a register
- */
-uchar i2c_reg_read(uchar i2c_addr, uchar reg)
-{
-       uchar buf;
-
-       i2c_read(i2c_addr, reg, 1, &buf, 1);
-
-       return(buf);
-}
-
-/*-----------------------------------------------------------------------
- * Write a register
- */
-void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
-{
-       i2c_write(i2c_addr, reg, 1, &val, 1);
-}