spi: omap3: fix claim/release bus within DM

[u-boot] / drivers / misc / ds4510.c

diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c
index 936fb3ead45e7b18538fd39abc82ffe6d4dd08d5..bf20a833ecdd620a77858e8d1373bf0be4c0d05f 100644 (file)
--- a/drivers/misc/ds4510.c
+++ b/drivers/misc/ds4510.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008 Extreme Engineering Solutions, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 /*
@@ -12,12 +11,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <command.h>
-#include <ds4510.h>
-
-/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_DS4510_ADDR
-#define CONFIG_SYS_I2C_DS4510_ADDR     (~0)
-#endif
+#include "ds4510.h"
 
 enum {
        DS4510_CMD_INFO,
@@ -35,7 +29,7 @@ enum {
 /*
  * Write to DS4510, taking page boundaries into account
  */
-int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
+static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
 {
        int wrlen;
        int i = 0;
@@ -64,7 +58,7 @@ int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
 /*
  * General read from DS4510
  */
-int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
+static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
 {
        return i2c_read(chip, offset, 1, buf, count);
 }
@@ -74,7 +68,7 @@ int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
  * nv = 0 - Writes to SEEPROM registers behave like EEPROM
  * nv = 1 - Writes to SEEPROM registers behave like SRAM
  */
-int ds4510_see_write(uint8_t chip, uint8_t nv)
+static int ds4510_see_write(uint8_t chip, uint8_t nv)
 {
        uint8_t data;
 
@@ -92,7 +86,7 @@ int ds4510_see_write(uint8_t chip, uint8_t nv)
 /*
  * Write de-assertion of reset signal delay
  */
-int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
+static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
 {
        uint8_t data;
 
@@ -108,7 +102,7 @@ int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
 /*
  * Write pullup characteristics of IO pins
  */
-int ds4510_pullup_write(uint8_t chip, uint8_t val)
+static int ds4510_pullup_write(uint8_t chip, uint8_t val)
 {
        val &= DS4510_IO_MASK;
 
@@ -118,7 +112,7 @@ int ds4510_pullup_write(uint8_t chip, uint8_t val)
 /*
  * Read pullup characteristics of IO pins
  */
-int ds4510_pullup_read(uint8_t chip)
+static int ds4510_pullup_read(uint8_t chip)
 {
        uint8_t val;
 
@@ -131,7 +125,7 @@ int ds4510_pullup_read(uint8_t chip)
 /*
  * Write drive level of IO pins
  */
-int ds4510_gpio_write(uint8_t chip, uint8_t val)
+static int ds4510_gpio_write(uint8_t chip, uint8_t val)
 {
        uint8_t data;
        int i;
@@ -155,7 +149,7 @@ int ds4510_gpio_write(uint8_t chip, uint8_t val)
 /*
  * Read drive level of IO pins
  */
-int ds4510_gpio_read(uint8_t chip)
+static int ds4510_gpio_read(uint8_t chip)
 {
        uint8_t data;
        int val = 0;
@@ -175,7 +169,7 @@ int ds4510_gpio_read(uint8_t chip)
 /*
  * Read physical level of IO pins
  */
-int ds4510_gpio_read_val(uint8_t chip)
+static int ds4510_gpio_read_val(uint8_t chip)
 {
        uint8_t val;
 
@@ -185,7 +179,6 @@ int ds4510_gpio_read_val(uint8_t chip)
        return val & DS4510_IO_MASK;
 }
 
-#ifdef CONFIG_CMD_DS4510
 /*
  * Display DS4510 information
  */
@@ -247,9 +240,7 @@ cmd_tbl_t cmd_ds4510[] = {
        U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""),
        U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""),
        U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""),
-#ifdef CONFIG_CMD_DS4510_RST
        U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""),
-#endif
        U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""),
        U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""),
        U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""),
@@ -257,7 +248,7 @@ cmd_tbl_t cmd_ds4510[] = {
 
 int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR;
+       static uint8_t chip = 0x51;
        cmd_tbl_t *c;
        ulong ul_arg2 = 0;
        ulong ul_arg3 = 0;
@@ -318,10 +309,8 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
                return ds4510_pullup_write(chip, tmp);
        case DS4510_CMD_INFO:
                return ds4510_info(chip);
-#ifdef CONFIG_CMD_DS4510_RST
        case DS4510_CMD_RSTDELAY:
                return ds4510_rstdelay_write(chip, ul_arg2);
-#endif
        case DS4510_CMD_EEPROM:
                end = DS4510_EEPROM + DS4510_EEPROM_SIZE;
                off = DS4510_EEPROM;
@@ -374,11 +363,9 @@ U_BOOT_CMD(
        "       - disable/enable pullup on specified pin\n"
        "ds4510 nv 0|1\n"
        "       - make gpio and seeprom writes volatile/non-volatile"
-#ifdef CONFIG_CMD_DS4510_RST
        "\n"
        "ds4510 rstdelay 0-3\n"
        "       - set reset output delay"
-#endif
        "\n"
        "ds4510 eeprom read addr off cnt\n"
        "ds4510 eeprom write addr off cnt\n"
@@ -390,4 +377,3 @@ U_BOOT_CMD(
        "ds4510 sram write addr off cnt\n"
        "       - read/write 'cnt' bytes at SRAM offset 'off'"
 );
-#endif /* CONFIG_CMD_DS4510 */