powerpc/usb: fix bug of CPU hang when missing USB PHY clock

[u-boot] / drivers / misc / fsl_law.c

diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index a71a0ce4267944c1f42874bb71b32b6c0ab553eb..223cd5d65c816aac52f969e05332a970b73e7e51 100644 (file)
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -275,25 +275,52 @@ void init_laws(void)
                                law_table[i].size, law_table[i].trgt_id);
        }
 
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
        /* check RCW to get which port is used for boot */
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        u32 bootloc = in_be32(&gur->rcwsr[6]);
-       /* in SRIO boot we need to set specail LAWs for SRIO interfaces */
+       /*
+        * in SRIO or PCIE boot we need to set specail LAWs for
+        * SRIO or PCIE interfaces.
+        */
        switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
+       case 0x0: /* boot from PCIE1 */
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_PCIE_1);
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_PCIE_1);
+               break;
+       case 0x1: /* boot from PCIE2 */
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_PCIE_2);
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_PCIE_2);
+               break;
+       case 0x2: /* boot from PCIE3 */
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_PCIE_3);
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+                               LAW_SIZE_1M,
+                               LAW_TRGT_IF_PCIE_3);
+               break;
        case 0x8: /* boot from SRIO1 */
-               set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
                                LAW_SIZE_1M,
                                LAW_TRGT_IF_RIO_1);
-               set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
                                LAW_SIZE_1M,
                                LAW_TRGT_IF_RIO_1);
                break;
        case 0x9: /* boot from SRIO2 */
-               set_next_law(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
                                LAW_SIZE_1M,
                                LAW_TRGT_IF_RIO_2);
-               set_next_law(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+               set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
                                LAW_SIZE_1M,
                                LAW_TRGT_IF_RIO_2);
                break;