ddr: altera: stratix10: Add DDR support for Stratix10 SoC

[u-boot] / drivers / misc / mxc_ocotp.c

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 0b1c05078f386092262824a895123371f474c70d..9ff475d9255dbefdec24fef374d77bbd5710ea2a 100644 (file)
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2013 ADVANSEE
  * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
@@ -8,8 +9,6 @@
  * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
  * which is:
  * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -18,7 +17,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/imx-common/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
 
 #define BO_CTRL_WR_UNLOCK              16
 #define BM_CTRL_WR_UNLOCK              0xffff0000
@@ -29,6 +28,14 @@
 #ifdef CONFIG_MX7
 #define BM_CTRL_ADDR                    0x0000000f
 #define BM_CTRL_RELOAD                  0x00000400
+#elif defined(CONFIG_MX7ULP)
+#define BM_CTRL_ADDR                    0x000000FF
+#define BM_CTRL_RELOAD                  0x00000400
+#define BM_OUT_STATUS_DED                              0x00000400
+#define BM_OUT_STATUS_LOCKED                   0x00000800
+#define BM_OUT_STATUS_PROGFAIL                 0x00001000
+#elif defined(CONFIG_MX8M)
+#define BM_CTRL_ADDR                   0x000000ff
 #else
 #define BM_CTRL_ADDR                   0x0000007f
 #endif
@@ -70,6 +77,12 @@
 #elif defined CONFIG_MX7
 #define FUSE_BANK_SIZE 0x40
 #define FUSE_BANKS     16
+#elif defined(CONFIG_MX7ULP)
+#define FUSE_BANK_SIZE 0x80
+#define FUSE_BANKS     31
+#elif defined(CONFIG_MX8M)
+#define FUSE_BANK_SIZE 0x40
+#define FUSE_BANKS     64
 #else
 #error "Unsupported architecture\n"
 #endif
@@ -98,7 +111,7 @@ u32 fuse_bank_physical(int index)
 {
        u32 phy_index;
 
-       if (is_mx6sl()) {
+       if (is_mx6sl() || is_mx7ulp()) {
                phy_index = index;
        } else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) {
                if ((is_mx6ull() || is_mx6sll()) && index == 8)
@@ -187,6 +200,10 @@ static int finish_access(struct ocotp_regs *regs, const char *caller)
        err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
        clear_error(regs);
 
+#ifdef CONFIG_MX7ULP
+       /* Need to power down the OTP memory */
+       writel(1, &regs->pdn);
+#endif
        if (err) {
                printf("mxc_ocotp %s(): Access protect error\n", caller);
                return -EIO;
@@ -217,6 +234,13 @@ int fuse_read(u32 bank, u32 word, u32 *val)
 
        *val = readl(&regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 
+#ifdef CONFIG_MX7ULP
+       if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
+               writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
+               printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
+               return -EIO;
+       }
+#endif
        return finish_access(regs, __func__);
 }
 
@@ -238,6 +262,12 @@ static void set_timing(struct ocotp_regs *regs)
        clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
                        timing);
 }
+#elif defined(CONFIG_MX7ULP)
+static void set_timing(struct ocotp_regs *regs)
+{
+       /* No timing set for MX7ULP */
+}
+
 #else
 static void set_timing(struct ocotp_regs *regs)
 {
@@ -268,6 +298,8 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
        u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 #ifdef CONFIG_MX7
        u32 addr = bank;
+#elif defined CONFIG_MX8M
+       u32 addr = bank << 2 | word;
 #else
        u32 addr;
        /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */
@@ -302,12 +334,37 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
        *val = readl(&regs->read_fuse_data);
 #endif
 
+#ifdef CONFIG_MX7ULP
+       if (readl(&regs->out_status) & BM_OUT_STATUS_DED) {
+               writel(BM_OUT_STATUS_DED, &regs->out_status_clr);
+               printf("mxc_ocotp %s(): fuse read wrong\n", __func__);
+               return -EIO;
+       }
+#endif
+
        return finish_access(regs, __func__);
 }
 
 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
                                const char *caller)
 {
+#ifdef CONFIG_MX7ULP
+       u32 val;
+       int ret;
+
+       /* Only bank 0 and 1 are redundancy mode, others are ECC mode */
+       if (bank != 0 && bank != 1) {
+               ret = fuse_sense(bank, word, &val);
+               if (ret)
+                       return ret;
+
+               if (val != 0) {
+                       printf("mxc_ocotp: The word has been programmed, no more write\n");
+                       return -EPERM;
+               }
+       }
+#endif
+
        return prepare_access(regs, bank, word, true, caller);
 }
 
@@ -355,6 +412,14 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 #endif
        udelay(WRITE_POSTAMBLE_US);
 
+#ifdef CONFIG_MX7ULP
+       if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
+               writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
+               printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
+               return -EIO;
+       }
+#endif
+
        return finish_access(regs, __func__);
 }
 
@@ -374,5 +439,13 @@ int fuse_override(u32 bank, u32 word, u32 val)
 
        writel(val, &regs->bank[phy_bank].fuse_regs[phy_word << 2]);
 
+#ifdef CONFIG_MX7ULP
+       if (readl(&regs->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) {
+               writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), &regs->out_status_clr);
+               printf("mxc_ocotp %s(): fuse write is failed\n", __func__);
+               return -EIO;
+       }
+#endif
+
        return finish_access(regs, __func__);
 }