imx6: icorem6_rqs: Update SPL board boot order for eMMC

[u-boot] / drivers / misc / mxs_ocotp.c

diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
index 1659ee6a5eecd9d2bb6a098a230c7e03394102ef..a42164cccdfed3ed8500245080972c4258ca7309 100644 (file)
--- a/drivers/misc/mxs_ocotp.c
+++ b/drivers/misc/mxs_ocotp.c
@@ -14,7 +14,7 @@
 
 #include <common.h>
 #include <fuse.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
@@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
                /* Return the original HCLK clock speed. */
                *val = readl(&clkctrl_regs->hw_clkctrl_hbus);
                *val &= CLKCTRL_HBUS_DIV_MASK;
+               *val >>= CLKCTRL_HBUS_DIV_OFFSET;
 
                /* Scale the HCLK to 454/19 = 23.9 MHz . */
                scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;
@@ -187,6 +188,8 @@ static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask)
        uint32_t hclk_val, vddio_val;
        int ret;
 
+       mxs_ocotp_clear_error();
+
        /* Make sure the banks are closed for reading. */
        ret = mxs_ocotp_read_bank_open(0);
        if (ret) {