i.MX28: Add cache support to MXS NAND driver

[u-boot] / drivers / misc / pmic_fsl.c

diff --git a/drivers/misc/pmic_fsl.c b/drivers/misc/pmic_fsl.c
index 13dde47fc869402c69cf0fc3254b3f20b2107197..0ff75ed76e506e6ffe249b15d2add731d1632a93 100644 (file)
--- a/drivers/misc/pmic_fsl.c
+++ b/drivers/misc/pmic_fsl.c
@@ -26,32 +26,38 @@
 #include <pmic.h>
 #include <fsl_pmic.h>
 
+#if defined(CONFIG_PMIC_SPI)
 static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
 {
-       if ((val == NULL) && (write))
-               return *val & ~(1 << 31);
-       else
-               return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
+       return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
 }
+#endif
 
 int pmic_init(void)
 {
        struct pmic *p = get_pmic();
        static const char name[] = "FSL_PMIC";
 
-       puts("Board PMIC init\n");
-
        p->name = name;
-       p->interface = PMIC_SPI;
        p->number_of_regs = PMIC_NUM_OF_REGS;
-       p->bus = CONFIG_FSL_PMIC_BUS;
 
+#if defined(CONFIG_PMIC_SPI)
+       p->interface = PMIC_SPI;
+       p->bus = CONFIG_FSL_PMIC_BUS;
        p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
        p->hw.spi.clk = CONFIG_FSL_PMIC_CLK;
        p->hw.spi.mode = CONFIG_FSL_PMIC_MODE;
        p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN;
        p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END;
        p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
+#elif defined(CONFIG_PMIC_I2C)
+       p->interface = PMIC_I2C;
+       p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
+       p->hw.i2c.tx_num = 3;
+       p->bus = I2C_PMIC;
+#else
+#error "You must select CONFIG_PMIC_SPI or CONFIG_PMIC_I2C"
+#endif
 
        return 0;
 }