powerpc/esdhc: Add 3.3v voltage support in esdhc capacity register

[u-boot] / drivers / mmc / dw_mmc.c

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 796a811876c7503faac7067f848eb994a68fd97c..1e0f72bbe7dcb75bfeeb5ed0a035b3945bf463e3 100644 (file)
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -11,6 +11,7 @@
 #include <mmc.h>
 #include <dwmmc.h>
 #include <asm-generic/errno.h>
+#include <asm/arch/dwmmc.h>
 
 #define PAGE_SIZE 4096
 
@@ -72,7 +73,7 @@ static void dwmci_prepare_data(struct dwmci_host *host,
                dwmci_set_idma_desc(cur_idmac, flags, cnt,
                                start_addr + (i * PAGE_SIZE));
 
-               if(blk_cnt < 8)
+               if (blk_cnt <= 8)
                        break;
                blk_cnt -= 8;
                cur_idmac++;
@@ -111,7 +112,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 {
        struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
        ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
-                                data ? data->blocks : 0);
+                                data ? DIV_ROUND_UP(data->blocks, 8) : 0);
        int flags = 0, i;
        unsigned int timeout = 100000;
        u32 retry = 10000;
@@ -220,12 +221,12 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
        if ((freq == host->clock) || (freq == 0))
                return 0;
        /*
-        * If host->mmc_clk didn't define,
+        * If host->get_mmc_clk didn't define,
         * then assume that host->bus_hz is source clock value.
         * host->bus_hz should be set from user.
         */
-       if (host->mmc_clk)
-               sclk = host->mmc_clk(host->dev_index);
+       if (host->get_mmc_clk)
+               sclk = host->get_mmc_clk(host->dev_index);
        else if (host->bus_hz)
                sclk = host->bus_hz;
        else {
@@ -301,6 +302,16 @@ static int dwmci_init(struct mmc *mmc)
        struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
        u32 fifo_size;
 
+       if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+               dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+               dwmci_writel(host, EMMCP_SEND0, 0);
+               dwmci_writel(host, EMMCP_CTRL0,
+                            MPSCTRL_SECURE_READ_BIT |
+                            MPSCTRL_SECURE_WRITE_BIT |
+                            MPSCTRL_NON_SECURE_READ_BIT |
+                            MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+       }
+
        dwmci_writel(host, DWMCI_PWREN, 1);
 
        if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {