uint scr; /* eSDHC control register */
};
+struct fsl_esdhc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
/**
* struct fsl_esdhc_priv
*
struct fsl_esdhc *esdhc_regs;
unsigned int sdhc_clk;
unsigned int bus_width;
- struct mmc_config cfg;
+#if !CONFIG_IS_ENABLED(BLK)
struct mmc *mmc;
+#endif
struct udevice *dev;
int non_removable;
int wp_enable;
static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
- int timeout = 1000;
+ ulong start;
/* Reset the entire host controller */
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
/* Wait until the controller is available */
- while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
- udelay(1000);
+ start = get_timer(0);
+ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
+ if (get_timer(start) > 1000)
+ return -ETIMEDOUT;
+ }
#if defined(CONFIG_FSL_USDHC)
/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
return 1;
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
if (priv->non_removable)
return 1;
#ifdef CONFIG_DM_GPIO
return 0;
}
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
static int esdhc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_priv *priv = mmc->priv;
.send_cmd = esdhc_send_cmd,
.set_ios = esdhc_set_ios,
};
+#endif
-static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
+ struct fsl_esdhc_plat *plat)
{
+ struct mmc_config *cfg;
struct fsl_esdhc *regs;
- struct mmc *mmc;
u32 caps, voltage_caps;
int ret;
esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
- memset(&priv->cfg, 0, sizeof(priv->cfg));
+ cfg = &plat->cfg;
+#ifndef CONFIG_DM_MMC
+ memset(cfg, '\0', sizeof(*cfg));
+#endif
voltage_caps = 0;
caps = esdhc_read32(®s->hostcapblt);
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
- priv->cfg.name = "FSL_SDHC";
- priv->cfg.ops = &esdhc_ops;
+ cfg->name = "FSL_SDHC";
+#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
+ cfg->ops = &esdhc_ops;
+#endif
#ifdef CONFIG_SYS_SD_VOLTAGE
- priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
+ cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
- priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
- if ((priv->cfg.voltages & voltage_caps) == 0) {
+ if ((cfg->voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
return -1;
}
if (priv->bus_width == 8)
- priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
else if (priv->bus_width == 4)
- priv->cfg.host_caps = MMC_MODE_4BIT;
+ cfg->host_caps = MMC_MODE_4BIT;
- priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
- priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
+ cfg->host_caps |= MMC_MODE_DDR_52MHz;
#endif
if (priv->bus_width > 0) {
if (priv->bus_width < 8)
- priv->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
if (priv->bus_width < 4)
- priv->cfg.host_caps &= ~MMC_MODE_4BIT;
+ cfg->host_caps &= ~MMC_MODE_4BIT;
}
if (caps & ESDHC_HOSTCAPBLT_HSS)
- priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
- priv->cfg.host_caps &= ~MMC_MODE_8BIT;
+ cfg->host_caps &= ~MMC_MODE_8BIT;
#endif
- priv->cfg.f_min = 400000;
- priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
+ cfg->f_min = 400000;
+ cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
- priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
-
- mmc = mmc_create(&priv->cfg, priv);
- if (mmc == NULL)
- return -1;
-
- priv->mmc = mmc;
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
struct fsl_esdhc_priv *priv)
{
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
+ struct fsl_esdhc_plat *plat;
struct fsl_esdhc_priv *priv;
+ struct mmc *mmc;
int ret;
if (!cfg)
priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
if (!priv)
return -ENOMEM;
+ plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+ if (!plat) {
+ free(priv);
+ return -ENOMEM;
+ }
ret = fsl_esdhc_cfg_to_priv(cfg, priv);
if (ret) {
debug("%s xlate failure\n", __func__);
+ free(plat);
free(priv);
return ret;
}
- ret = fsl_esdhc_init(priv);
+ ret = fsl_esdhc_init(priv, plat);
if (ret) {
debug("%s init failure\n", __func__);
+ free(plat);
free(priv);
return ret;
}
+ mmc = mmc_create(&plat->cfg, priv);
+ if (!mmc)
+ return -EIO;
+
+ priv->mmc = mmc;
+
return 0;
}
}
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
#include <asm/arch/clock.h>
__weak void init_clk_usdhc(u32 index)
{
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- int node = dev_of_offset(dev);
#ifdef CONFIG_DM_REGULATOR
struct udevice *vqmmc_dev;
#endif
fdt_addr_t addr;
unsigned int val;
+ struct mmc *mmc;
int ret;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->esdhc_regs = (struct fsl_esdhc *)addr;
priv->dev = dev;
- val = fdtdec_get_int(fdt, node, "bus-width", -1);
+ val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
priv->bus_width = 8;
else if (val == 4)
else
priv->bus_width = 1;
- if (fdt_get_property(fdt, node, "non-removable", NULL)) {
+ if (dev_read_bool(dev, "non-removable")) {
priv->non_removable = 1;
} else {
priv->non_removable = 0;
#ifdef CONFIG_DM_GPIO
- gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
- 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+ GPIOD_IS_IN);
#endif
}
priv->wp_enable = 1;
#ifdef CONFIG_DM_GPIO
- ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
- &priv->wp_gpio, GPIOD_IS_IN);
+ ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ GPIOD_IS_IN);
if (ret)
priv->wp_enable = 0;
#endif
return -EINVAL;
}
- ret = fsl_esdhc_init(priv);
+ ret = fsl_esdhc_init(priv, plat);
if (ret) {
dev_err(dev, "fsl_esdhc_init failure\n");
return ret;
}
- upriv->mmc = priv->mmc;
- priv->mmc->dev = dev;
+ mmc = &plat->mmc;
+ mmc->cfg = &plat->cfg;
+ mmc->dev = dev;
+ upriv->mmc = mmc;
- return 0;
+ return esdhc_init_common(priv, mmc);
}
+#if CONFIG_IS_ENABLED(DM_MMC_OPS)
+static int fsl_esdhc_get_cd(struct udevice *dev)
+{
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return true;
+ return esdhc_getcd_common(priv);
+}
+
+static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int fsl_esdhc_set_ios(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+ return esdhc_set_ios_common(priv, &plat->mmc);
+}
+
+static const struct dm_mmc_ops fsl_esdhc_ops = {
+ .get_cd = fsl_esdhc_get_cd,
+ .send_cmd = fsl_esdhc_send_cmd,
+ .set_ios = fsl_esdhc_set_ios,
+};
+#endif
+
static const struct udevice_id fsl_esdhc_ids[] = {
{ .compatible = "fsl,imx6ul-usdhc", },
{ .compatible = "fsl,imx6sx-usdhc", },
{ /* sentinel */ }
};
+#if CONFIG_IS_ENABLED(BLK)
+static int fsl_esdhc_bind(struct udevice *dev)
+{
+ struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+
+ return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
+
U_BOOT_DRIVER(fsl_esdhc) = {
.name = "fsl-esdhc-mmc",
.id = UCLASS_MMC,
.of_match = fsl_esdhc_ids,
+#if CONFIG_IS_ENABLED(DM_MMC_OPS)
+ .ops = &fsl_esdhc_ops,
+#endif
+#if CONFIG_IS_ENABLED(BLK)
+ .bind = fsl_esdhc_bind,
+#endif
.probe = fsl_esdhc_probe,
+ .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
};
#endif
projects / u-boot / blobdiff