usb: dwc3: Add DWC3 controller driver support

[u-boot] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5e270dd57df6ba67b4a4c71ff08b9d7705d375e..c4719e6f3635b6396ea731c8c624199d17cdc335 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -56,7 +56,7 @@ struct fsl_esdhc {
        uint    adsaddr;        /* ADMA system address register */
        char    reserved2[100]; /* reserved */
        uint    vendorspec;     /* Vendor Specific register */
-       char    reserved3[59];  /* reserved */
+       char    reserved3[56];  /* reserved */
        uint    hostver;        /* Host controller version register */
        char    reserved4[4];   /* reserved */
        uint    dmaerraddr;     /* DMA error address register */
@@ -105,7 +105,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        else if (cmd->resp_type & MMC_RSP_PRESENT)
                xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
+       defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
        if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
                xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -183,7 +184,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        int timeout;
        struct fsl_esdhc_cfg *cfg = mmc->priv;
        struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-
+#ifdef CONFIG_LS2085A
+       dma_addr_t addr;
+#endif
        uint wml_value;
 
        wml_value = data->blocksize/4;
@@ -194,7 +197,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+               addr = virt_to_phys((void *)(data->dest));
+               if (upper_32_bits(addr))
+                       printf("Error found for upper 32 bits\n");
+               else
+                       esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
+#endif
 #endif
        } else {
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
@@ -212,7 +223,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
                                        wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+               addr = virt_to_phys((void *)(data->src));
+               if (upper_32_bits(addr))
+                       printf("Error found for upper 32 bits\n");
+               else
+                       esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
                esdhc_write32(&regs->dsaddr, (u32)data->src);
+#endif
 #endif
        }
 
@@ -259,10 +278,23 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
        (struct mmc_cmd *cmd,
         struct mmc_data *data) {
+#ifdef CONFIG_LS2085A
+       unsigned start = 0;
+#else
        unsigned start = (unsigned)data->dest ;
+#endif
        unsigned size = roundup(ARCH_DMA_MINALIGN,
                                data->blocks*data->blocksize);
        unsigned end = start+size ;
+#ifdef CONFIG_LS2085A
+       dma_addr_t addr;
+
+       addr = virt_to_phys((void *)(data->dest));
+       if (upper_32_bits(addr))
+               printf("Error found for upper 32 bits\n");
+       else
+               start = lower_32_bits(addr);
+#endif
        invalidate_dcache_range(start, end);
 }
 #endif
@@ -355,9 +387,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
        /* Workaround for ESDHC errata ENGcm03648 */
        if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
-               int timeout = 2500;
+               int timeout = 6000;
 
-               /* Poll on DATA0 line for cmd with busy signal for 250 ms */
+               /* Poll on DATA0 line for cmd with busy signal for 600 ms */
                while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
                                        PRSSTAT_DAT0)) {
                        udelay(100);
@@ -474,11 +506,47 @@ static void set_sysctl(struct mmc *mmc, uint clock)
        esdhc_setbits32(&regs->sysctl, clk);
 }
 
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+static void esdhc_clock_control(struct mmc *mmc, bool enable)
+{
+       struct fsl_esdhc_cfg *cfg = mmc->priv;
+       struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+       u32 value;
+       u32 time_out;
+
+       value = esdhc_read32(&regs->sysctl);
+
+       if (enable)
+               value |= SYSCTL_CKEN;
+       else
+               value &= ~SYSCTL_CKEN;
+
+       esdhc_write32(&regs->sysctl, value);
+
+       time_out = 20;
+       value = PRSSTAT_SDSTB;
+       while (!(esdhc_read32(&regs->prsstat) & value)) {
+               if (time_out == 0) {
+                       printf("fsl_esdhc: Internal clock never stabilised.\n");
+                       break;
+               }
+               time_out--;
+               mdelay(1);
+       }
+}
+#endif
+
 static void esdhc_set_ios(struct mmc *mmc)
 {
        struct fsl_esdhc_cfg *cfg = mmc->priv;
        struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+       /* Select to use peripheral clock */
+       esdhc_clock_control(mmc, false);
+       esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
+       esdhc_clock_control(mmc, true);
+#endif
        /* Set the clock speed */
        set_sysctl(mmc, mmc->clock);
 
@@ -620,7 +688,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
                return -1;
        }
 
-       cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+       cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
        cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
 #endif
@@ -662,6 +730,39 @@ int fsl_esdhc_mmc_init(bd_t *bis)
        return fsl_esdhc_initialize(bis, cfg);
 }
 
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+void mmc_adapter_card_type_ident(void)
+{
+       u8 card_id;
+       u8 value;
+
+       card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
+       gd->arch.sdhc_adapter = card_id;
+
+       switch (card_id) {
+       case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
+               break;
+       case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+               break;
+       case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
+               value = QIXIS_READ(brdcfg[5]);
+               value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
+               QIXIS_WRITE(brdcfg[5], value);
+               break;
+       case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
+               break;
+       case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
+               break;
+       case QIXIS_ESDHC_ADAPTER_TYPE_SD:
+               break;
+       case QIXIS_ESDHC_NO_ADAPTER:
+               break;
+       default:
+               break;
+       }
+}
+#endif
+
 #ifdef CONFIG_OF_LIBFDT
 void fdt_fixup_esdhc(void *blob, bd_t *bd)
 {
@@ -675,9 +776,17 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
        }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+       do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+                              gd->arch.sdhc_clk, 1);
+#else
        do_fixup_by_compat_u32(blob, compat, "clock-frequency",
                               gd->arch.sdhc_clk, 1);
-
+#endif
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+       do_fixup_by_compat_u32(blob, compat, "adapter-type",
+                              (u32)(gd->arch.sdhc_adapter), 1);
+#endif
        do_fixup_by_compat(blob, compat, "status", "okay",
                           4 + 1, 1);
 }