mmc: all hosts support 1-bit bus width and legacy timings

[u-boot] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index cc188c4260737c4fa29a399f410ba939ab09b67f..cca57f8a79dbc48b75f0b5063751fd65465aec8d 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -171,20 +171,20 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
        uint databuf;
        uint size;
        uint irqstat;
-       uint timeout;
+       ulong start;
 
        if (data->flags & MMC_DATA_READ) {
                blocks = data->blocks;
                buffer = data->dest;
                while (blocks) {
-                       timeout = PIO_TIMEOUT;
+                       start = get_timer(0);
                        size = data->blocksize;
                        irqstat = esdhc_read32(&regs->irqstat);
-                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
-                               && --timeout);
-                       if (timeout <= 0) {
-                               printf("\nData Read Failed in PIO Mode.");
-                               return;
+                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
+                               if (get_timer(start) > PIO_TIMEOUT) {
+                                       printf("\nData Read Failed in PIO Mode.");
+                                       return;
+                               }
                        }
                        while (size && (!(irqstat & IRQSTAT_TC))) {
                                udelay(100); /* Wait before last byte transfer complete */
@@ -200,14 +200,14 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
                blocks = data->blocks;
                buffer = (char *)data->src;
                while (blocks) {
-                       timeout = PIO_TIMEOUT;
+                       start = get_timer(0);
                        size = data->blocksize;
                        irqstat = esdhc_read32(&regs->irqstat);
-                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
-                               && --timeout);
-                       if (timeout <= 0) {
-                               printf("\nData Write Failed in PIO Mode.");
-                               return;
+                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
+                               if (get_timer(start) > PIO_TIMEOUT) {
+                                       printf("\nData Write Failed in PIO Mode.");
+                                       return;
+                               }
                        }
                        while (size && (!(irqstat & IRQSTAT_TC))) {
                                udelay(100); /* Wait before last byte transfer complete */
@@ -665,7 +665,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 #endif
 
        /* Set the initial clock speed */
-       mmc_set_clock(mmc, 400000);
+       mmc_set_clock(mmc, 400000, false);
 
        /* Disable the BRR and BWR bits in IRQSTAT */
        esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);