/*
- * Copyright 2007,2010 Freescale Semiconductor, Inc
+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+ xfertyp |= XFERTYP_AC12EN;
+#endif
}
if (data->flags & MMC_DATA_READ)
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
+#ifdef CONFIG_MX53
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ xfertyp |= XFERTYP_CMDTYP_ABORT;
+#endif
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}
/*
* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
*/
-static int
+static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
struct fsl_esdhc *regs = mmc->priv;
&& --timeout);
if (timeout <= 0) {
printf("\nData Read Failed in PIO Mode.");
- return timeout;
+ return;
}
while (size && (!(irqstat & IRQSTAT_TC))) {
udelay(100); /* Wait before last byte transfer complete */
}
} else {
blocks = data->blocks;
- buffer = data->src;
+ buffer = (char *)data->src;
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
&& --timeout);
if (timeout <= 0) {
printf("\nData Write Failed in PIO Mode.");
- return timeout;
+ return;
}
while (size && (!(irqstat & IRQSTAT_TC))) {
udelay(100); /* Wait before last byte transfer complete */
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
- uint wml_value;
int timeout;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ uint wml_value;
-#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
- if (!(data->flags & MMC_DATA_READ)) {
- if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
- printf("\nThe SD card is locked. "
- "Can not write to a locked card.\n\n");
- return TIMEOUT;
- }
- esdhc_write32(®s->dsaddr, (u32)data->src);
- } else
- esdhc_write32(®s->dsaddr, (u32)data->dest);
-#else
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
- if (wml_value > 0x10)
- wml_value = 0x10;
+ if (wml_value > WML_RD_WML_MAX)
+ wml_value = WML_RD_WML_MAX_VAL;
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(®s->dsaddr, (u32)data->dest);
} else {
- if (wml_value > 0x80)
- wml_value = 0x80;
+ if (wml_value > WML_WR_WML_MAX)
+ wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;
wml_value << 16);
esdhc_write32(®s->dsaddr, (u32)data->src);
}
-#endif
+#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
+ if (!(data->flags & MMC_DATA_READ)) {
+ if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+ printf("\nThe SD card is locked. "
+ "Can not write to a locked card.\n\n");
+ return TIMEOUT;
+ }
+ esdhc_write32(®s->dsaddr, (u32)data->src);
+ } else
+ esdhc_write32(®s->dsaddr, (u32)data->dest);
+#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
/* Calculate the timeout period for data transactions */
- timeout = fls(mmc->tran_speed/10) - 1;
+ /*
+ * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
+ * 2)Timeout period should be minimum 0.250sec as per SD Card spec
+ * So, Number of SD Clock cycles for 0.25sec should be minimum
+ * (SD Clock/sec * 0.25 sec) SD Clock cycles
+ * = (mmc->tran_speed * 1/4) SD Clock cycles
+ * As 1) >= 2)
+ * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
+ * Taking log2 both the sides
+ * => timeout + 13 >= log2(mmc->tran_speed/4)
+ * Rounding up to next power of 2
+ * => timeout + 13 = log2(mmc->tran_speed/4) + 1
+ * => timeout + 13 = fls(mmc->tran_speed/4)
+ */
+ timeout = fls(mmc->tran_speed/4);
timeout -= 13;
if (timeout > 14)
if (timeout < 0)
timeout = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+ if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+ timeout++;
+#endif
+
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ return 0;
+#endif
+
esdhc_write32(®s->irqstat, -1);
sync();
do {
irqstat = esdhc_read32(®s->irqstat);
- if (irqstat & DATA_ERR)
- return COMM_ERR;
-
if (irqstat & IRQSTAT_DTOE)
return TIMEOUT;
+
+ if (irqstat & DATA_ERR)
+ return COMM_ERR;
} while (!(irqstat & IRQSTAT_TC) &&
(esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
#endif
int ret = 0;
u8 card_absent;
- /* Enable cache snooping */
- if (cfg && !cfg->no_snoop)
- esdhc_write32(®s->scr, 0x00000040);
-
/* Reset the entire host controller */
esdhc_write32(®s->sysctl, SYSCTL_RSTA);
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
+ /* Enable cache snooping */
+ if (cfg && !cfg->no_snoop)
+ esdhc_write32(®s->scr, 0x00000040);
+
esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */
- set_sysctl(mmc, 400000);
+ mmc_set_clock(mmc, 400000);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
{
struct fsl_esdhc *regs;
struct mmc *mmc;
- u32 caps;
+ u32 caps, voltage_caps;
if (!cfg)
return -1;
mmc->set_ios = esdhc_set_ios;
mmc->init = esdhc_init;
+ voltage_caps = 0;
caps = regs->hostcapblt;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
+ caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
+ ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+#endif
if (caps & ESDHC_HOSTCAPBLT_VS18)
- mmc->voltages |= MMC_VDD_165_195;
+ voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)
- mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
+ voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
if (caps & ESDHC_HOSTCAPBLT_VS33)
- mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
+ voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+#ifdef CONFIG_SYS_SD_VOLTAGE
+ mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
+#else
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+#endif
+ if ((mmc->voltages & voltage_caps) == 0) {
+ printf("voltage not supported by controller\n");
+ return -1;
+ }
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
- mmc->f_max = MIN(gd->sdhc_clk, 50000000);
+ mmc->f_max = MIN(gd->sdhc_clk, 52000000);
mmc_register(mmc);
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
const char *compat = "fsl,esdhc";
- const char *status = "okay";
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
if (!hwconfig("esdhc")) {
- status = "disabled";
- goto out;
+ do_fixup_by_compat(blob, compat, "status", "disabled",
+ 8 + 1, 1);
+ return;
}
+#endif
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
gd->sdhc_clk, 1);
-out:
- do_fixup_by_compat(blob, compat, "status", status,
- strlen(status) + 1, 1);
+
+ do_fixup_by_compat(blob, compat, "status", "okay",
+ 4 + 1, 1);
}
#endif
projects / u-boot / blobdiff