mvsata: issue hard reset on initialization

[u-boot] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d01c926c4554debbe4fc6e61239d49cfbfc40ab0..ec953f07d7156760b2ca81e5ee6418efdc91b14b 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -99,6 +99,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        else if (cmd->resp_type & MMC_RSP_PRESENT)
                xfertyp |= XFERTYP_RSPTYP_48;
 
+#ifdef CONFIG_MX53
+       if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+               xfertyp |= XFERTYP_CMDTYP_ABORT;
+#endif
        return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
@@ -178,14 +182,14 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        wml_value = data->blocksize/4;
 
        if (data->flags & MMC_DATA_READ) {
-               if (wml_value > 0x10)
-                       wml_value = 0x10;
+               if (wml_value > WML_RD_WML_MAX)
+                       wml_value = WML_RD_WML_MAX_VAL;
 
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
        } else {
-               if (wml_value > 0x80)
-                       wml_value = 0x80;
+               if (wml_value > WML_WR_WML_MAX)
+                       wml_value = WML_WR_WML_MAX_VAL;
                if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
                        printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
                        return TIMEOUT;
@@ -210,7 +214,21 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 
        /* Calculate the timeout period for data transactions */
-       timeout = fls(mmc->tran_speed/10) - 1;
+       /*
+        * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
+        * 2)Timeout period should be minimum 0.250sec as per SD Card spec
+        *  So, Number of SD Clock cycles for 0.25sec should be minimum
+        *              (SD Clock/sec * 0.25 sec) SD Clock cycles
+        *              = (mmc->tran_speed * 1/4) SD Clock cycles
+        * As 1) >=  2)
+        * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
+        * Taking log2 both the sides
+        * => timeout + 13 >= log2(mmc->tran_speed/4)
+        * Rounding up to next power of 2
+        * => timeout + 13 = log2(mmc->tran_speed/4) + 1
+        * => timeout + 13 = fls(mmc->tran_speed/4)
+        */
+       timeout = fls(mmc->tran_speed/4);
        timeout -= 13;
 
        if (timeout > 14)
@@ -219,6 +237,11 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        if (timeout < 0)
                timeout = 0;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+       if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+               timeout++;
+#endif
+
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 
        return 0;
@@ -313,11 +336,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
                do {
                        irqstat = esdhc_read32(&regs->irqstat);
 
-                       if (irqstat & DATA_ERR)
-                               return COMM_ERR;
-
                        if (irqstat & IRQSTAT_DTOE)
                                return TIMEOUT;
+
+                       if (irqstat & DATA_ERR)
+                               return COMM_ERR;
                } while (!(irqstat & IRQSTAT_TC) &&
                                (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
 #endif
@@ -502,6 +525,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        mmc->f_min = 400000;
        mmc->f_max = MIN(gd->sdhc_clk, 52000000);
 
+       mmc->b_max = 0;
        mmc_register(mmc);
 
        return 0;